PIC18F8680-E/PT Microchip Technology, PIC18F8680-E/PT Datasheet - Page 2

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PIC18F8680-E/PT

Manufacturer Part Number
PIC18F8680-E/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8680-E/PT

Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3328 B
Interface Type
I2C, SPI, AUSART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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PIC18F6585/6680/8585/8680
6. Module: Enhanced Controller Area
7. Module: Enhanced Controller Area
8. Module: ADC
DS80162E-page 2
In Mode 2, the FIFOEMPTY bit (COMSTAT<7>) is
not automatically cleared upon a FIFO empty
condition.
Work around
Clear FIFOEMPTY bit twice after reading any
message from FIFO. FIFOEMPTY will remain set
if FIFO is still not empty.
Date Codes that pertain to this issue:
All engineering and production devices.
Bits 7 and 6 in the COMSTAT register are swapped
for write operation. As a result, performing an
individual set/clear bit operation on bit 6 in the
COMSTAT register actually sets/clears bit 7 and
vice versa. Note that the read operation will read
the correct bit.
Work around
If individual bit clear operation is required, first make
sure that the desired bit is not already cleared. If the
bit is set, use the swapped bit position. For exam-
ple, use ‘BCF COMSTAT, 6’ to clear bit 7. If the bit
is already cleared, do not clear it again.
If possible, operate on the entire register using
‘MOVWF, MOVFF, CLRF’, etc. instructions.
Date Codes that pertain to this issue:
All engineering and production devices.
A/D conversion does not start if the device is put to
Sleep during the auto-acquisition period. As a
result, the device will need another wake-up event
source to wake-up from Sleep.
Work around
Do not use the auto-acquisition feature when A/D
conversion during Sleep is required.
Date Codes that pertain to this issue:
All engineering and production devices.
Network (ECAN™ Technology)
Network (ECAN™ Technology)
9. Module: Core (Instruction Set)
EXAMPLE 1:
10. Module: Enhanced Controller Area
The Decimal Adjust W register instruction, DAW, may
improperly clear the Carry (C) bit (STATUS<0>)
when executed.
Work around
Test the Carry bit state before executing the DAW
instruction. If the Carry bit is set, increment the
next higher byte to be added using an instruction
such as INCFSZ (this instruction does not affect
any Status flags and will not overflow a BCD nib-
ble). After the DAW instruction has been executed,
process the Carry bit normally (see Example 1).
This is repeated for each DAW instruction.
Date Codes that pertain to this issue:
All engineering and production devices.
The behavior of the Phase Segment 2 Select bit
(SEG2PHTS) in the BRGCON2 register is
inverted. As a result, when Phase Segment 2 is
less than Phase Segment 1, or IPT, the actual bit
rate will not be correct.
Work around
1. Use SEG2PHTS = 0 for freely programmable
2. Select Phase Segment 2 such that it is greater
Date Codes that pertain to this issue:
All engineering and production devices.
MOVLW
ADDLW
BTFSC
INCFSZ byte2
DAW
BTFSC
INCFSZ byte2
and ‘1’ for maximum of Phase Segment 1 or
Information Processing Time (IPT), whichever
is greater.
or equal to Phase Segment 1.
0x80
0x80
STATUS, C
STATUS, C
Network (ECAN™ Technology)
PROCESSING THE CARRY
BIT DURING BCD ADDITIONS
© 2007 Microchip Technology Inc.
; .80 (BCD)
; .80 (BCD)
; test C
; inc next higher LSB
; test C
; inc next higher LSB

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