AT32UC3B0128-A2UT Atmel, AT32UC3B0128-A2UT Datasheet - Page 224
![IC MCU AVR32 128KB FLASH 64-TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0128-A2UT
Manufacturer Part Number
AT32UC3B0128-A2UT
Description
IC MCU AVR32 128KB FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0128-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
44
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0128-A2UT
Manufacturer:
XILINX
Quantity:
150
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19.10.6
Figure 19-9. Master Read with One Data Byte
Figure 19-10. Master Read with Multiple Data Bytes
19.10.7
32059K–03/2011
TXCOMP
RXRDY
TWD
Master Receiver Mode
Internal Address
S
Write START Bit
DADR
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in MMR). During the acknowledge
clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it
down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (RHR). The RXRDY bit is reset when reading the RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without IADR, the STOP bit must be set after the next-to-last data received.
See
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
TXCOMP
RXRDY
R
Figure
TWD
A
19-10. For Internal Address usage see
S
DATA n
Write START &
STOP Bit
DADR
Read RHR
A
DATA n
DATA (n+1)
R
A
A
DATA (n+1)
Read RHR
DATA
DATA (n+m)-1
Figure
”Internal Address” on page
Read RHR
N
19-9. When a multiple data byte read is
DATA (n+m)-1
P
A
Read RHR
after next-to-last data read
DATA (n+m)
Write STOP Bit
Figure
AT32UC3B
224.
19-9. When the
N
DATA (n+m)
Read RHR
P
224
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