AT32UC3B0128-A2UT Atmel, AT32UC3B0128-A2UT Datasheet - Page 553

• Manufacturer Part Number: AT32UC3B0128-A2UT
• Description: IC MCU AVR32 128KB FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0128-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 25-3. GOVRE and OVREn Flag Behavior
32059K–03/2011
OVRE0(SR)
GOVRE(SR)
DRDY(ASR)
CH0(CHSR)
CH1(CHSR)
TRIGGER
EOC0(SR)
EOC1(SR)
LCDR
CRD0
CRD1
Undefined Data
Undefined Data
If the CDR register is not read before further incoming data is converted, the corresponding
Overrun Error bit in the SR register (SR.OVREn) is set.
In the same way, new data converted when DRDY is high sets the General Overrun Error bit in
the SR register (SR.GOVRE).
The OVREn and GOVRE bits are automatically cleared when the SR register is read.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in SR are unpredictable.
Conversion
Undefined Data
Conversion
Data A
Data A
Data B
Conversion
Data B
Data C
AT32UC3B
Data C
Read CDR1
Read CDR0
Read SR
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