DSPIC30F6010A-20E/PF Microchip Technology, DSPIC30F6010A-20E/PF Datasheet
DSPIC30F6010A-20E/PF
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DSPIC30F6010A-20E/PF Summary of contents
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... Family Silicon Errata and Data Sheet Clarification The dsPIC30F6010A/6015 family devices that you have received conform functionally to the current Device Data Sheet (DS70150D), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1 ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number CPU 1. DISI Instruction Output — 2. Compare Output PWM Mode 3. Compare QEI Index Pulse 4. Reset Mode ADC Sleep Mode 5. ADC Sampling 6. Rate QEI Interrupt 7. Generation Sleep — 8. Mode 2 I C™ Slave Mode 9. PWM Debug Mode 10 ...
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... Consumption in Sleep Mode Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. dsPIC30F6010A/6015 Issue Summary 2 When the I C module is enabled, the dsPIC generates a glitch on the SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration ...
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... Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A4). 1. Module: CPU When a user executes a DISI #7, for example, this will disable interrupts for cycles (7 + the DISI instruction itself) ...
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... © 2010 Microchip Technology Inc. dsPIC30F6010A/6015 5. Module: ADC ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. This means that if the ADC is configured to generate an interrupt after a certain number of INT0 triggered conversions, the ADC conversions will not be triggered and the device will remain in Sleep ...
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... Module: ADC The maximum sampling rate for the 10-bit Analog- to-Digital Conversion module is 750 ksps. This rate is only achievable when one A/D pin is being used. Configuring the ADC module to use multiple sample-and-hold circuits (see device data sheet), will not improve the conversion speed of the module ...
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... IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2010 Microchip Technology Inc. dsPIC30F6010A/6015 Work around To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. In addition, a global variable could be used to keep track of bit 15, so that when an overflow or underflow condition is present on POSCNT, the variable will toggle bit 15 ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, implement any of the following three work arounds, depending on the application requirements ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2010 Microchip Technology Inc. dsPIC30F6010A/6015 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condi- tion is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6010A/6015 14. Module: PLL The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. Work around The user application must include an oscillator failure trap service routine ...
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... Module 10-bit Addressing mode, some address matches don’t set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, following exceptions: • ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6010A/6015 22. Module: ADC If the ADC module enabled state when the device enters Sleep mode as a result of executing a PWRSAV #0 instruction, the device power-down current (I ) may exceed the specifications listed PD in the device data sheet. This may happen even if the ADC module is disabled by clearing the ADON bit prior to entering Sleep mode ...
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... Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70150D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: DC Characteristics: I/O Pin Input ...
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... Operations), 16-18 (I (CAN). This document replaces the following errata documents: • DS80258, “dsPIC30F6010A/6015 Rev. A2/A3 Silicon Errata” • DS80400, “dsPIC30F6010A/6015 Rev. A4 Silicon Errata” Rev B Document (8/2009) Added silicon issues 20 (QEI) and 21 (QEI). Rev C Document (6/2010) Added silicon issues 22 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). © ...
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... NOTES: DS80458C-page 16 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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