DSPIC30F6010A-20E/PF Microchip Technology, DSPIC30F6010A-20E/PF Datasheet - Page 5

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DSPIC30F6010A-20E/PF

Manufacturer Part Number
DSPIC30F6010A-20E/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F6010A-20E/PF

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
4.5V To 5.5V
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F6010A-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
4. Module: QEI
© 2010 Microchip Technology Inc.
The Index Pulse Reset mode of the Quadrature
Encoder Interface (QEI) does not work properly
when used along with count error detection. When
counting upwards, the POSCNT register will incre-
ment one extra count after the index pulse is
received. The extra count will generate a false
count error interrupt.
Work around
There are multiple work arounds for this issue,
depending on the specific requirements of the
application:
1. Ignore count error interrupts when the counting
2. The user may disable count error interrupts by
3. The user may disable the index pulse reset
Affected Silicon Revisions
A2
X
direction is upwards and the POSCNT register
has the value of MAXCNT + 1.
setting the CEID bit in the DFLTCON register.
feature
(QEICON<2>). Writing QEICON = 0x0600 will
provide a QEI interrupt each time an index
pulse is received, but the POSCNT register will
not be modified. The POSCNT register value
can be read in the QEI interrupt handler and
used as an offset value to calculate the
absolute position of the encoder disc with
respect to the index pulse.
A3
X
by
A4
X
clearing
the
POSRES
bit
5. Module: ADC
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero. This means that if the ADC is
configured to generate an interrupt after a certain
number of INT0 triggered conversions, the ADC
conversions will not be triggered and the device
will remain in Sleep. The ADC will perform
conversions and wake-up the device only if it is
configured to generate an interrupt after each INT0
triggered conversion (SMPI<3:0> = 0000).
Work around
None. If ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> to ‘0000’ (interrupt
on every conversion).
Affected Silicon Revisions
A2
X
dsPIC30F6010A/6015
A3
X
A4
X
DS80458C-page 5

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