PIC18F4685-I/PT Microchip Technology, PIC18F4685-I/PT Datasheet - Page 479

• Manufacturer Part Number: PIC18F4685-I/PT
• Description: IC PIC MCU FLASH 48KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4685-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3328 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Diagrams and Specifications ................................ 437
© 2009 Microchip Technology Inc.
SPI Mode (Slave Mode with CKE = 0) ..................... 196
SPI Mode (Slave Mode with CKE = 1) ..................... 196
Stop Condition Receive or Transmit Mode .............. 222
Synchronous Reception (Master Mode, SREN) ...... 246
Synchronous Transmission ...................................... 244
Synchronous Transmission
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 441
Transition for Entry to Idle Mode ................................ 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 40
Transition for Wake From Sleep (HSPLL) ................. 39
Transition From RC_RUN Mode
Transition From SEC_RUN Mode
Transition to RC_RUN Mode ..................................... 38
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 439
EUSART Synchronous Receive Requirements ....... 452
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
(Through TXEN) .............................................. 245
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 357
to PRI_RUN Mode ............................................. 38
to PRI_RUN Mode (HSPLL) .............................. 37
Internal RC Accuracy ....................................... 438
(All CCP Modules) ........................................... 442
(Master Mode, CKE = 0) .................................. 444
(Master Mode, CKE = 1) .................................. 445
(Slave Mode, CKE = 0) .................................... 446
(MCLR Not Tied to V
Requirements ................................................. 452
DD
DD
) ........................................... 49
, V
DD
DD
DD
), Case 1 ....................... 48
), Case 2 ...................... 48
Rise Tpwrt) ................ 48
PIC18F2682/2685/4682/4685
Top-of-Stack Access .......................................................... 64
TRISE Register
TSTFSZ ........................................................................... 405
Two-Speed Start-up ................................................. 345, 357
Two-Word Instructions
TXSTA Register
V
Voltage Reference Specifications .................................... 433
W
Watchdog Timer (WDT) ........................................... 345, 355
WCOL ...................................................... 217, 218, 219, 222
WCOL Status Flag ................................... 217, 218, 219, 222
WWW Address ................................................................ 481
WWW, On-Line Support ...................................................... 7
X
XORLW ........................................................................... 405
XORWF ........................................................................... 406
Example SPI Mode Requirements
External Clock Requirements .................................. 437
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 438
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
PSPMODE Bit ......................................................... 140
Example Cases ......................................................... 68
BRGH Bit ................................................................. 233
Associated Registers ............................................... 356
Control Register ....................................................... 355
Programming Considerations .................................. 355
2
2
C Bus Data Requirements (Slave Mode) .............. 449
C Bus Start/Stop Bits Requirements
(Slave Mode, CKE = 1) .................................... 447
(Slave Mode) ................................................... 448
(PIC18F4682/4685) ......................................... 443
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 440
Clock Requirements ........................................ 441
2
2
C Bus Data Requirements ................ 451
C Bus Start/Stop Bits Requirements . 450
DS39761C-page 479