ATSAM3U2CA-AU Atmel, ATSAM3U2CA-AU Datasheet - Page 859

• Manufacturer Part Number: ATSAM3U2CA-AU
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U2CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: SAM3U
• No. Of I/o's: 57
• Ram Memory Size: 36KB
• Cpu Speed: 96MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 36 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

37.13.19 HSMCI Write Protect Status Register
Name:
Address:
Access:
• WP_VS: Write Protection Violation Status
• WP_VSRC: Write Protection Violation SouRCe
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write
access has been attempted.
6430D–ATARM–25-Mar-11
Value
31
23
15
0
1
2
3
–
7
–
RESET
WRITE
NONE
Name
BOTH
30
22
14
HSMCI_WPSR
0x400000E8
Read-only
–
6
–
Description
No Write Protection Violation occurred since the last read of this
register (WP_SR)
Write Protection detected unauthorized attempt to write a control
register had occurred (since the last read.)
Software reset had been performed while Write Protection was
enabled (since the last read).
Both Write Protection violation and software reset with Write
Protection enabled have occurred since the last read.
29
21
13
–
5
–
28
20
12
–
4
–
WP_VSRC
WP_VSRC
27
19
11
–
3
26
18
10
–
2
WP_VS
SAM3U Series
25
17
–
9
1
24
16
–
8
0
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