DSPIC30F6010T-30I/PF Microchip Technology, DSPIC30F6010T-30I/PF Datasheet
DSPIC30F6010T-30I/PF
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DSPIC30F6010T-30I/PF Summary of contents
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... Microchip Technology Inc. dsPIC30F6010 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70119E ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions single cycle • ± 16-bit single-cycle shift © 2006 Microchip Technology Inc. dsPIC30F6010 Peripheral Features: • High current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters ...
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... Low power consumption Output Motor EEPROM Timer Input Comp/Std Control Bytes 16-bit Cap PWM PWM 1024 1024 1024 1024 1024 1024 4096 ADC 10-bit Quad 1 Msps Enc 6 ch Yes Yes Yes Yes Yes Yes Yes © 2006 Microchip Technology Inc. ...
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... PWM4H/RE7 4 T2CK/RC1 5 T4CK/RC3 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 FLTA/INT1/RE8 13 FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 *dsPIC30F6010A recommended for new designs. © 2006 Microchip Technology Inc. dsPIC30F6010 dsPIC30F6010 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS70119E-page 4 © 2006 Microchip Technology Inc. ...
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... Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157). © 2006 Microchip Technology Inc. dsPIC30F6010 This document contains device specific information for the dsPIC30F6010 device. The dsPIC30F devices ...
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... OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/UPDN/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15 PORTD PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 FLTA/INT1/RE8 FLTB/INT2/RE9 PORTE C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 PORTF © 2006 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. Description Analog input channels. AN0 and AN1 are also used for device programming data and clock inputs, respectively ...
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... ST buffer when configured in RC mode; CMOS otherwise. Timer1 external clock input. Timer2 external clock input. Timer4 external clock input. Analog = Analog input C™ Output = Power © 2006 Microchip Technology Inc. ...
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... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. Description UART1 Receive. UART1 Transmit. UART2 Receive. UART2 Transmit. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. Analog Voltage Reference (High) input. ...
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... NOTES: DS70119E-page 10 © 2006 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2006 Microchip Technology Inc. dsPIC30F6010 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...
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... The upper byte of the SR register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. © 2006 Microchip Technology Inc. ...
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... AD39 DSP ACCA Accumulators ACCB PC22 7 0 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2006 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
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... Unsigned divide: Wm/Wn W0; Rem A block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-2: Instruction CLR ED EDAC MAC MOVSAC MPY which MPY.N MSC selection W1 W1 W0; Rem DSP INSTRUCTION SUMMARY Algebraic Operation – – change – – © 2006 Microchip Technology Inc. ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2006 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array dsPIC30F6010 Round u Logic Zero Backfill DS70119E-page 15 ...
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... OVBTE) in the INTCON1 register (refer to Section 5.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain. © 2006 Microchip Technology Inc. ...
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... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2006 Microchip Technology Inc. dsPIC30F6010 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY ...
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... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is pre- sented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2006 Microchip Technology Inc. ...
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... TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, Read/Write instruc- tions, bit 23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2006 Microchip Technology Inc. dsPIC30F6010 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR ...
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... Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory. DS70119E-page 20 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2006 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2006 Microchip Technology Inc. dsPIC30F6010 A set of Table Instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the least significant word of the program address ...
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... Execution in the last iteration - Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle © 2006 Microchip Technology Inc. ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2006 Microchip Technology Inc. dsPIC30F6010 Program Space 0x0000 (1) PSVPAG ...
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... Optionally Mapped into Program Memory 0xFFFF DS70119E-page 24 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 0x1FFE Y Data RAM (Y) 0x27FE 0x2800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2006 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2006 Microchip Technology Inc. dsPIC30F6010 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read Only ...
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... FIGURE 3-8: MSB 15 Byte 1 0001 0x0000 Byte 3 0003 0x0000 Byte 5 0005 0x0000 ® DATA ALIGNMENT LSB Byte 0 0000 Byte 2 0002 Byte 4 0004 © 2006 Microchip Technology Inc. ...
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... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2006 Microchip Technology Inc. dsPIC30F6010 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70119E-page 30 © 2006 Microchip Technology Inc. ...
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... Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2006 Microchip Technology Inc. 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buff- ers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode, (i.e., address bound- ary checks will be performed on both the lower and upper address boundaries). © 2006 Microchip Technology Inc. ...
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... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2006 Microchip Technology Inc. dsPIC30F6010 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... W register that has been designated as the bit-reversed pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer N bytes, should not be enabled © 2006 Microchip Technology Inc. ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 2048 1024 512 256 128 © 2006 Microchip Technology Inc. Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value dsPIC30F6010 A0 Decimal ...
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... NOTES: DS70119E-page 36 © 2006 Microchip Technology Inc. ...
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... The INTCON2 register controls the external inter- rupt request signal behavior and the use of the alternate vector table. © 2006 Microchip Technology Inc. dsPIC30F6010 Note: Interrupt Flag bits get set when an inter- rupt condition occurs, regardless of the state of its corresponding Enable bit ...
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... C2 – Combined IRQ for CAN2 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 LVD – Low-Voltage Detect 43 51 FLTA – PWM Fault FLTB – PWM Fault B 45-53 53-61 Reserved Lowest Natural Order Priority © 2006 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected, which may result in malfunction. • Trap Lockout: Occurrence of multiple Trap conditions simultaneously will cause a Reset. © 2006 Microchip Technology Inc. dsPIC30F6010 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1 ...
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... Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector © 2006 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
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... The RETFIE (Return from Interrupt) instruction will unstack the program counter and status registers to return the processor to its state prior to the interrupt sequence. © 2006 Microchip Technology Inc. 5.5 Alternate Vector Table In Program Memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 5-1 ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT — — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. dsPIC30F6010 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 6.6 “Programming Operations” for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2006 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2006 Microchip Technology Inc. dsPIC30F6010 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2006 Microchip Technology Inc. ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70119E-page 48 © 2006 Microchip Technology Inc. ...
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... The write typically requires complete, but the write time will vary with voltage and temperature. © 2006 Microchip Technology Inc. A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- sible for waiting for the appropriate duration of time before initiating another data EEPROM write/erase operation ...
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... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2006 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2006 Microchip Technology Inc. dsPIC30F6010 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. © 2006 Microchip Technology Inc. ...
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... WR LAT + WR Port Read LAT Read Port © 2006 Microchip Technology Inc. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Typically this instruction would be a NOP will be OL EXAMPLE 8-1: MOV 0xFF00, W0; Configure PORTB<15:8> inputs MOV W0, TRISBB; and PORTB<7:0> as outputs NOP ; Delay 1 cycle btssPORTB, #13; Next Instruction I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE © 2006 Microchip Technology Inc. ...
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TABLE 8-1: dsPIC30F6010 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 — — PORTA 02C2 RA15 RA14 — — LATA 02C4 LATA15 LATA14 — — TRISB 02C6 TRISB15 TRISB14 TRISB13 ...
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... Bit 1 Bit 0 Reset State CN1IE CN0IE 0000 0000 0000 0000 CN17IE CN16IE 0000 0000 0000 0000 CN1PUE CN0PUE 0000 0000 0000 0000 0000 0000 0000 0000 © 2006 Microchip Technology Inc. ...
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... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit period register match or falling edge of external gate signal © 2006 Microchip Technology Inc. dsPIC30F6010 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module ...
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... When a match between the timer and the period regis- ter occurs, an interrupt can be generated, if the respective Timer Interrupt Enable bit is asserted. TCKPS<1:0> TSYNC Sync 1 0 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 © 2006 Microchip Technology Inc. ...
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... XTAL SOSCO pF 100K © 2006 Microchip Technology Inc. dsPIC30F6010 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the period register, and is then reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for ...
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... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2006 Microchip Technology Inc. dsPIC30F6010 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer ...
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... Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70119E-page 62 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 x Gate 0 1 Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2006 Microchip Technology Inc. ...
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... Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER) ADC Event Trigger Equal Comparator x 16 Reset 0 T3IF Event Flag 1 TGATE T3CK © 2006 Microchip Technology Inc. PR2 Comparator x 16 TMR2 Q D TGATE Gate Sync PR3 TMR3 Q ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>). © 2006 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70119E-page 66 © 2006 Microchip Technology Inc. ...
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... T4CK Note: Timer Configuration bit T32, T4CON(<3>) must be set to ‘ control bits are respective to the T4CON register. © 2006 Microchip Technology Inc. dsPIC30F6010 The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are listed below: • ...
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... ADC Event Trigger Equal Reset 0 T5IF Event Flag 1 TGATE T5CK DS70119E-page 68 PR4 TMR4 Q D TGATE Q CK TON 1 x Gate Sync PR5 Comparator x 16 TMR5 Q D TGATE CK Q Sync Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2006 Microchip Technology Inc. ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70119E-page 70 © 2006 Microchip Technology Inc. ...
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... ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2006 Microchip Technology Inc. 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • ...
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... Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx Status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The Capture Interrupt Enable bit is located in the corresponding IEC Control register. © 2006 Microchip Technology Inc. ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70119E-page 74 © 2006 Microchip Technology Inc. ...
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... TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2006 Microchip Technology Inc. The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2006 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. © 2006 Microchip Technology Inc. When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
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... PCDOUT Existing Pin Logic 0 UPDN Up/Down 1 © 2006 Microchip Technology Inc. The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode • ...
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... Position counter reset by detection of index pulse, QEIM<2:0> = 110. 2. Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. © 2006 Microchip Technology Inc. ...
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... The UPDN Control/Status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. © 2006 Microchip Technology Inc. dsPIC30F6010 In addition, control bit UPDN_SRC (QEICON<0>) determines whether the timer count direction state is based on the logic state, written into the UPDN Control/ Status bit (QEICON< ...
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... The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 Status register. Enabling an interrupt is accomplished via the respec- tive Enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. © 2006 Microchip Technology Inc. ...
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TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB PCDOUT TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 0000 ...
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... NOTES: DS70119E-page 84 © 2006 Microchip Technology Inc. ...
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... Three Phase AC Induction Motor • Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS) © 2006 Microchip Technology Inc. dsPIC30F6010 The PWM module has the following features: • 8 PWM I/O pins with 4 duty cycle generators • 16-bit resolution • ...
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... PWM Generator Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR PWM4H PWM4L PWM3H Output Generator and PWM3L Override Logic Driver Block PWM2H Generator and PWM2L Override Logic PWM1H PWM1L FLTA FLTB Special Event Trigger © 2006 Microchip Technology Inc. ...
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... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2006 Microchip Technology Inc. dsPIC30F6010 15.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...
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... PWM pin will be inactive for the entire PWM period. In addition, the out- put on the PWM pin will be active for the entire PWM period if the value in the duty cycle register is greater than the value held in the PTPER register. © 2006 Microchip Technology Inc. using ...
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... FIGURE 15-3: CENTER-ALIGNED PWM Period/2 PTPER Duty Cycle 0 Period © 2006 Microchip Technology Inc. dsPIC30F6010 15.5 PWM Duty Cycle Comparison Units There are four 16-bit special function registers (PDC1, PDC2, PDC3 and PDC4) used to specify duty cycle values for the PWM module. ...
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... On a load of the down timer due to a duty cycle comparison edge event. • write to the DTCON1 or DTCON2 registers. • On any device Reset. Note: The user should not modify the DTCON1 or DTCON2 values while the PWM mod- ule is operating (PTEN = 1). Unexpected results may occur. © 2006 Microchip Technology Inc ...
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... PTPER register occurs, the PTMR reg- ister is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2006 Microchip Technology Inc. dsPIC30F6010 Time selected by DTSxI bit ( 15.10 PWM Output Override ...
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... PWM cycle or half-cycle boundary. The operating mode for each Fault input pin is selected using the FLTAM and FLTBM control bits in the FLTACON and FLTBCON Special Function Registers. Each of the Fault pins can be controlled manually in software. © 2006 Microchip Technology Inc. ...
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... PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. © 2006 Microchip Technology Inc. dsPIC30F6010 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio ...
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TABLE 15-2: 8-OUTPUT PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PTMOD4 PTMOD3 ...
Page 97
... The module will not respond to SCL transitions while SPIROV is 1, effectively disabling the module until SPIxBUF is read by user software. © 2006 Microchip Technology Inc. dsPIC30F6010 Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer is completed, the contents of the shift register (SPIxSR) is moved to the receive buffer ...
Page 98
... Shift clock Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Secondary Primary F Prescaler Prescaler CY 1:1-1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2006 Microchip Technology Inc. ...
Page 99
... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been deasserted in the middle of a transmit/receive. © 2006 Microchip Technology Inc. dsPIC30F6010 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut-down ...
Page 100
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend uninitialized bit Note: ...
Page 101
... I2CRCV is the receive buffer, as shown in Figure 16-1. I2CTRN is the transmit register to which bytes are writ- ten during a transmit operation, as shown in Figure 16-2. © 2006 Microchip Technology Inc. • Serial clock synchronization for I used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). ...
Page 102
... DS70119E-page 100 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2006 Microchip Technology Inc. ...
Page 103
... SCL high (see timing diagram). The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2006 Microchip Technology Inc. dsPIC30F6010 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, Receive mode is initiated ...
Page 104
... C module generates two interrupt flags, MI2CIF Master Interrupt Flag) and SI2CIF (I rupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. © 2006 Microchip Technology Inc Slave Inter- ...
Page 105
... The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start © 2006 Microchip Technology Inc. condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
Page 106
... For the I C, the I2CSIDL bit selects if the module stops or continues on Idle. If I2CSIDL = 0, the module contin- ues operation on assertion of the Idle mode. If I2CSIDL = 1, the module stops on Idle bus is free, C OPERATION DURING CPU C OPERATION DURING CPU IDLE © 2006 Microchip Technology Inc ...
Page 107
TABLE 17- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...
Page 108
... NOTES: DS70119E-page 106 © 2006 Microchip Technology Inc. ...
Page 109
... Internal Data Bus UTXBRK Data UxTX Parity Note © 2006 Microchip Technology Inc. 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • ...
Page 110
... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16X Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA Control Signals UxRXIF © 2006 Microchip Technology Inc. ...
Page 111
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2006 Microchip Technology Inc. dsPIC30F6010 18.3 Transmitting Data 18.3.1 ...
Page 112
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2006 Microchip Technology Inc. RXB) ...
Page 113
... The URXISEL control bit does not have any impact on interrupt generation in this mode, since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. © 2006 Microchip Technology Inc. dsPIC30F6010 18.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...
Page 114
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2006 Microchip Technology Inc. ...
Page 115
TABLE 18-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG 0212 ...
Page 116
... NOTES: DS70119E-page 114 © 2006 Microchip Technology Inc. ...
Page 117
... Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low power Sleep and Idle mode © 2006 Microchip Technology Inc. dsPIC30F6010 The CAN bus module consists of a protocol engine, and message buffering/control. The CAN protocol engine handles all functions for receiving and transmit- ting messages on the CAN bus ...
Page 118
... RXF2 A Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit ErrPas BusOff Error Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX © 2006 Microchip Technology Inc. ...
Page 119
... Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2006 Microchip Technology Inc. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 120
... End-of-Frame (EOF) field. Reading the RXnIF flag will indicate which receive buffer caused the interrupt. • Wake-up interrupt The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. © 2006 Microchip Technology Inc. ...
Page 121
... TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag automatically cleared. © 2006 Microchip Technology Inc. dsPIC30F6010 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. ...
Page 122
... definition, the Nominal Bit Time has a minimum and a maximum the minimum nominal bit time is 1 sec, corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point . Also, by definition, Q Sync © 2006 Microchip Technology Inc. ...
Page 123
... The following requirement must be fulfilled while setting the lengths of the Phase Segments: • Propagation Segment + Phase1 Seg > = Phase2 Seg © 2006 Microchip Technology Inc. 19.6.5 SAMPLE POINT The Sample Point is the point of time at which the bus level is read and interpreted as the value of that respec tive bit ...
Page 124
TABLE 19-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — C1RXF0SID 0300 C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier <5:0> — — — C1RXF1SID ...
Page 125
TABLE 19-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B1 0356 Transmit Buffer 1 Byte 1 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C ...
Page 126
TABLE 19-2: CAN2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 — — — C2RXF0SID 03C0 C2RXF0EIDH 03C2 — — — — C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier <5:0> — — — C2RXF1SID ...
Page 127
TABLE 19-2: CAN2 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C2TX1B4 041C Transmit Buffer 1 Byte 7 C2TX1CON 041E — — — — C2TX0SID 0420 Transmit Buffer 0 Standard Identifier <10:6> C2TX0EID 0422 ...
Page 128
... NOTES: DS70119E-page 126 © 2006 Microchip Technology Inc. ...
Page 129
... The ADC has a unique feature of REF REF being able to operate while the device is in Sleep mode. © 2006 Microchip Technology Inc. dsPIC30F6010 The ADC module has six 16-bit registers: • ADC Control Register1 (ADCON1) • ADC Control Register2 (ADCON2) • ADC Control Register3 (ADCON3) • ...
Page 130
... AN13 AN14 AN14 AN15 AN15 AN1 DS70119E-page 128 CH1 ADC S/H - 10-bit Result + CH2 S/H - 16-word, 10-bit + CH3 S/H CH1,CH2, - CH3,CH0 sample input switches + CH0 S/H - © 2006 Microchip Technology Inc. Conversion Logic Dual Port Buffer Sample/Sequence Control Input Mux Control ...
Page 131
... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2006 Microchip Technology Inc. The CHPS bits selects how many channels are sam- pled. This can vary from channels. If CHPS selects 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 132
... AD . The source of the A/D CONVERSION CLOCK * (0.5 * (ADCS<5:0> ADCS<5:0> – time AD = 5V). Refer to the Section 24.0 DD under AD A/D CONVERSION CLOCK CALCULATION T = 154 nsec nsec (30 MIPS – 154 nsec = 2 • – nsec = 8. (ADCS<5:0> nsec = ( 165 nsec © 2006 Microchip Technology Inc. ...
Page 133
... Up to 153. 500 ksps Up to 256. 300 ksps Note 1: External V - and V REF REF circuit. © 2006 Microchip Technology Inc. R Max V Temperature S DD 500 4.5V to 5.5V -40°C to +85°C 500 4.5V to 5.5V -40°C to +85°C 500 3.0V to 5.5V -40°C to +125°C 5 ...
Page 134
... ADCON1 register • Enable sequential sampling by clearing the SIMSAM bit in the ADCON1 register • Enable at least two sample and hold channels by writing the CHPS<1:0> control bits in the 0 0 and V - pins following REF REF © 2006 Microchip Technology Inc. ...
Page 135
... The analog input multiplexer must be configured so that the same input pin is connected to © 2006 Microchip Technology Inc. both sample and hold channels. The A/D converts the value held on one S/H channel, while the second S/H channel acquires a new input sample ...
Page 136
... Refer to the Electrical Specifications for T time requirements 250 IC Sampling Switch leakage V = 0.6V T 500 nA period between conversions to SAMP and sample HOLD = DAC capacitance = 4 negligible if Rs £ 5 kW. PIN © 2006 Microchip Technology Inc. ...
Page 137
... Integer 0 © 2006 Microchip Technology Inc. If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...
Page 138
... Any external components connected (via high impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. and V as ESD the input voltage exceeds this SS © 2006 Microchip Technology Inc. ...
Page 139
TABLE 20-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ...
Page 140
... NOTES: DS70119E-page 138 © 2006 Microchip Technology Inc. ...
Page 141
... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2006 Microchip Technology Inc. dsPIC30F6010 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 142
... RC Oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70119E-page 140 Description (1) . (2) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2006 Microchip Technology Inc. ...
Page 143
... FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2006 Microchip Technology Inc. dsPIC30F6010 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer Switching and Control ...
Page 144
... OSC2 FPR1 FPR0 Function CLKO CLKO OSC2 0 0 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 X OSC2 1 X — — (Notes 1, 2) — — (Notes 1, 2) — — (Notes 1, 2) © 2006 Microchip Technology Inc. ...
Page 145
... Microchip Technology Inc. TUN<3:0> Bits 1001 1000 21.2.6 LOW POWER RC OSCILLATOR (LPRC) The LPRC oscillator is a component of the Watchdog Fout Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT and clock monitor circuits ...
Page 146
... Byte Write “0x78” to OSCCON high • Byte Write “0x9A” to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2006 Microchip Technology Inc. ...
Page 147
... Reset state. The POR also selects the device clock source identified by the oscil- lator configuration fuses. © 2006 Microchip Technology Inc. Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the resump- tion of normal operation ...
Page 148
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70119E-page 146 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2006 Microchip Technology Inc. ...
Page 149
... Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2006 Microchip Technology Inc. dsPIC30F6010 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 150
... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70119E-page 148 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2006 Microchip Technology Inc. ...
Page 151
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2006 Microchip Technology Inc. 21.6 Power Saving Modes There are two power saving states that can be entered through the execution of a special instruction, PWRSAV. ...
Page 152
... For additional infor- mation, please refer to the programming specifications of the device. Note: If the code protection configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V 4.5V. DD © 2006 Microchip Technology Inc. ...
Page 153
... MPLAB IDE. These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2006 Microchip Technology Inc. dsPIC30F6010 In each case, the selected EMUD pin is the Emulation/ Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line ...
Page 154
TABLE 21-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name . RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — — COSC<1:0> — PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD ...
Page 155
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. dsPIC30F6010 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 156
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2006 Microchip Technology Inc. ...
Page 157
... Microchip Technology Inc. dsPIC30F6010 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 158
... SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. © 2006 Microchip Technology Inc. ® ...
Page 159
... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2006 Microchip Technology Inc. Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modi- fier) or file register (specified by the value of ‘ ...
Page 160
... Programmer’s Reference Manual” (DS70157). Description {W13, [W13]+=2} {0x0000...0x1FFF} {0,1} {0...15} {0...31} {0...255} {0...255} for Byte mode, {0:1023} for Word mode {0...16384} {0...65535} {0...8388608}; LSB must be 0 {-512...511} {-32768...32767} {-16...16} © 2006 Microchip Technology Inc. {0...15} ...
Page 161
... Y data space prefetch address register for DSP instructions Wy {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions Wyd © 2006 Microchip Technology Inc. dsPIC30F6010 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0 ...
Page 162
... Branch if accumulator A overflow Branch if accumulator B overflow Branch if Overflow Branch if accumulator A saturated Branch if accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2006 Microchip Technology Inc Status Flags cycle Affected OA,OB,SA, C,DC,N,OV,Z ...
Page 163
... DAW DAW Wn 26 DEC DEC f DEC f,WREG DEC Ws,Wd © 2006 Microchip Technology Inc. dsPIC30F6010 # of Description words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 164
... Link frame pointer f = Logical Right Shift f WREG = Logical Right Shift Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Multiply and Accumulate Square and Accumulate © 2006 Microchip Technology Inc Status Flags cycle Affected C,DC,N,OV,Z ...
Page 165
... Wn 59 RESET RESET 60 RETFIE RETFIE 61 RETLW RETLW #lit10,Wn 62 RETURN RETURN © 2006 Microchip Technology Inc. dsPIC30F6010 # of Description words Move Move Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ ...
Page 166
... lit10 lit5 WREG - (C) WREG = f - WREG - ( lit10 - ( ( lit5 - ( WREG - f WREG = WREG - lit5 - WREG - f - (C) WREG = WREG - lit5 - nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> © 2006 Microchip Technology Inc Status Flags cycle Affected C,N C,N C,N N N,Z ...
Page 167
... XOR XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2006 Microchip Technology Inc. dsPIC30F6010 # of Description words Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Status Flags cycle Affected ...
Page 168
... NOTES: DS70119E-page 166 © 2006 Microchip Technology Inc. ...
Page 169
... Microchip Technology Inc. (except V and MCLR) (Note 1) .................................... -0. .......................................................................................................... ± > ...................................................................................................± the MCLR/V pin, inducing currents greater than 80 mA, may cause latchup. ...
Page 170
... INT Typ Max Unit Notes 50 °C °C/W 1 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- © 2006 Microchip Technology Inc. ...
Page 171
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2006 Microchip Technology Inc. dsPIC30F6010 ) DD Standard Operating Conditions: 2.5V to 5.5V ...
Page 172
... Industrial +125°C for Extended 0.128 MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS © 2006 Microchip Technology Inc. ...
Page 173
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2006 Microchip Technology Inc. dsPIC30F6010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° ...
Page 174
... T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions SMbus disabled DD V SMbus enabled SMbus disabled V SMbus enabled 5V PIN PIN DD Pin at high-impedance PIN DD Pin at high-impedance PIN XT PIN DD and LP Osc mode © 2006 Microchip Technology Inc. ...
Page 175
... These parameters are characterized but not tested in manufacturing. FIGURE 24-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) © 2006 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C (1) Min Typ Max (2) — ...
Page 176
... V — — V — — V — 2.65 V — 2.86 V — 2.97 V — 3.18 V — 3.50 V — 3.71 V — 3.82 V — 4.03 V — 4.24 V — 4.45 V — 4.77 V — — V (Device not in Brown-out Reset) Power Up Time-out © 2006 Microchip Technology Inc. ...
Page 177
... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T (1) Min ...
Page 178
... Operating voltage V range as described in DC Spec Section 24.1. DD Load Condition 2 - for OSC2 Pin 464 for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 +85°C for Industrial A +125°C for Extended OS31 OS31 OS41 © 2006 Microchip Technology Inc. ...
Page 179
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2006 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 180
... DD T +125° 3 +85° 4 +125° 4 +85° 3 +125° 3 +85° 4 +125° 4 +85° 3 +85° 4 +125° 4 © 2006 Microchip Technology Inc. ...
Page 181
... Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift percentages. TABLE 24-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65 Note 1: Change of LPRC frequency as V © 2006 Microchip Technology Inc. (3) MIPS MIPS (2) ( sec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1 ...
Page 182
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1)(2)(3) (4) Min Typ Max — — — — — — CY +85°C for Industrial +125°C for Extended Units Conditions ns — ns — ns — — — . OSC © 2006 Microchip Technology Inc. ...
Page 183
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F6010 SY10 SY20 SY13 SY13 DS70119E-page 181 ...
Page 184
... Band Gap Stable T +85°C for Industrial A T +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13>Status bit © 2006 Microchip Technology Inc. ...
Page 185
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2006 Microchip Technology Inc. dsPIC30F6010 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 186
... N = prescale value (1, 8, 64, 256) 1.5 T — +85°C for Industrial A +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2006 Microchip Technology Inc. ...
Page 187
... TQCP Input Period TQ20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F6010 TQ10 TQ11 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40° ...
Page 188
... A T +125°C for Extended A Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions ns See parameter D032 ns See parameter D031 © 2006 Microchip Technology Inc. ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 190
... T -40°C T (1) (2) Min Typ Max Units — — — ns — — — ns — — — — ns +85°C for Industrial A +125°C for Extended A Conditions See parameter D032 See parameter D031 — — © 2006 Microchip Technology Inc. ...
Page 191
... Note 1: These parameters are characterized but not tested in manufacturing Index Channel Digital Filter Clock Divide Select Bits. Refer to the “Quadrature Encoder Interface (QEI)” section in the “dsPIC30F Family Reference Manual” (DS70046). © 2006 Microchip Technology Inc. TQ36 TQ30 TQ31 TQ35 ...
Page 192
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1) Min Max Units — — — CY +85°C for Industrial +125°C for Extended Conditions 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) ns — © 2006 Microchip Technology Inc. ...
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... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2006 Microchip Technology Inc. SP10 SP21 SP20 BIT14 - - - - - -1 MSb SP30 ...
Page 194
... T +125°C for Extended A Max Units Conditions — ns — — ns — — ns See parameter D032 — ns See parameter D031 — ns See parameter D032 — ns See parameter D031 30 ns — — ns — — ns — — ns — © 2006 Microchip Technology Inc. ...
Page 195
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2006 Microchip Technology Inc. SP70 SP72 SP73 SP72 SP73 ...
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... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 24-3 for load conditions. DS70119E-page 194 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN SP52 SP72 SP73 SP51 © 2006 Microchip Technology Inc. ...
Page 197
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2006 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
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... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 24-3 for load conditions. DS70119E-page 196 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 © 2006 Microchip Technology Inc. ...
Page 199
... BRG is the value of the I C Baud Rate Generator. Refer to the “Inter-Integrated Circuit™ the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2006 Microchip Technology Inc. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
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... MHz s Device must operate at a minimum of 10 MHz. µs — µs Device must operate at a minimum of 1.5 MHz µs Device must operate at a minimum of 10 MHz µs — specified to be from 400 specified to be from 400 © 2006 Microchip Technology Inc. ...