AT91SAM9260B-CU Atmel, AT91SAM9260B-CU Datasheet - Page 16

• Manufacturer Part Number: AT91SAM9260B-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Cpu Family: 91S
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 180MHz
• Interface Type: 2-Wire/EBI/SPI/USART
• Total Internal Ram Size: 8KB
• # I/os (max): 96
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• On-chip Adc: 4-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 217
• Package Type: LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 210 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 96
• Ram Memory Size: 8KB
• Cpu Speed: 180MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

7.2
16
Bus Matrix
AT91SAM9260
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
• 8-Kbyte Data Cache, 8-Kbyte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
each quarter of the page
system flexibility
32-bit data interface
(Words)
or fixed default master
internal boot, one for external boot, one after remap
6221JS–ATARM–17-Jul-09