AT91SAM9260B-CU Atmel, AT91SAM9260B-CU Datasheet - Page 27

IC ARM9 MCU 217-LFBGA

AT91SAM9260B-CU

Manufacturer Part Number
AT91SAM9260B-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM9260B-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Cpu Family
91S
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
180MHz
Interface Type
2-Wire/EBI/SPI/USART
Total Internal Ram Size
8KB
# I/os (max)
96
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
On-chip Adc
4-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
217
Package Type
LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
4 KB
Maximum Clock Frequency
210 MHz
Number Of Programmable I/os
96
Number Of Timers
5
Operating Supply Voltage
2 V to 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
Minimum Operating Temperature
- 40 C
Controller Family/series
AT91SAM9xxx
No. Of I/o's
96
Ram Memory Size
8KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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9.2
9.3
9.4
6221JS–ATARM–17-Jul-09
Reset Controller
Shutdown Controller
Clock Generator
• Based on two Power-on-reset cells
• Status of the last reset
• Controls the internal resets and the NRST pin output
• Shutdown and Wake-up logic
• Embeds a Low-power 32,768 Hz Slow Clock Oscillator and a Low-power RC oscillator
• Embeds the Main Oscillator
• Embeds 2 PLLs
selectable with OSCSEL signal
– One on VDDBU and one on VDDCORE
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
– Allows shaping a reset signal for the external devices
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
– Provides the permanent Slow Clock SLCK to the system
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
– PLLA outputs 80 to 240 MHz clock
– PLLB outputs 70 to 130 MHz clock
– Both integrate an input divider to increase output accuracy
– PLLB embeds its own filter
reset, user reset or watchdog reset
AT91SAM9260
27

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