ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 17

• Manufacturer Part Number: ATMEGA2560V-8AU
• Description: IC AVR MCU 256K 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2560V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• A/d Inputs: 16-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 86
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Timers: 2-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Package: 100TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.1
6.6.2
6.7
2549M–AVR–09/10
Instruction Execution Timing
RAMPZ – Extended Z-pointer Register for ELPM/SPM
EIND – Extended Indirect Register
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 6-4. Note that LPM is not affected by the RAMPZ setting.
Figure 6-4.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation
of EIND, ZH, and ZL, as shown in Figure 6-5. Note that ICALL and IJMP are not affected by the
EIND setting.
Figure 6-5.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 6-6 on page 18
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit
0x3B (0x5B)
Read/Write
Initial Value
Bit (
Individually)
Bit (Z-pointer)
Bit
0x3C (0x5C)
Read/Write
Initial Value
Bit (Individual-
ly)
Bit
pointer)
(Indirect-
RAMPZ7
EIND7
The Z-pointer used by ELPM and SPM
The Indirect-pointer used by EICALL and EIJMP
R/W
R/W
7
0
7
0
23
23
7
7
RAMPZ6
EIND6
shows the parallel instruction fetches and instruction executions enabled
R/W
R/W
EIND
RAMPZ
6
0
6
0
RAMPZ5
EIND5
R/W
R/W
ATmega640/1280/1281/2560/2561
16
5
0
5
0
0
16
0
CPU
, directly generated from the selected clock source for the
RAMPZ4
EIND4
R/W
R/W
4
0
4
0
15
7
15
7
RAMPZ3
EIND3
R/W
R/W
ZH
3
0
3
0
ZH
RAMPZ2
EIND2
R/W
R/W
2
0
2
0
0
8
0
8
RAMPZ1
EIND1
R/W
R/W
1
0
1
0
7
7
7
7
RAMPZ0
EIND0
R/W
R/W
ZL
0
0
0
0
ZL
RAMPZ
EIND
0
0
0
0
17