ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 52

IC AVR MCU 256K 8MHZ 100TQFP

ATMEGA2560V-8AU

Manufacturer Part Number
ATMEGA2560V-8AU
Description
IC AVR MCU 256K 8MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA2560V-8AU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
A/d Inputs
16-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
4K Bytes
Input Output
86
Interface
2-Wire/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Timers
2-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Package
100TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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10. Power Management and Sleep Modes
10.1
Table 10-1.
Notes:
10.2
2549M–AVR–09/10
Extended Standby
Sleep Mode
Power-down
Power-save
Standby
ADCNRM
Sleep Modes
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
Idle Mode
Idle
(1)
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
F i g u r e 9 - 1 o n p a g e 4 0
ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an
appropriate sleep mode.
sources.
To enter any of the sleep modes, the SE bit in
56
SM0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP instruc-
tion. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Inter-
face, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and
X
Table 10-2 on page 56
X
X
X
X
X
X
(2)
CPU
Table 10-1
and clk
Oscillators
X
X
X
X
ATmega640/1280/1281/2560/2561
for a summary.
p r e s e n t s t h e d i f f e r e n t c l o c k s y s t e m s i n t h e
FLASH
X
X
X
X
(2)
(2)
(2)
(2)
shows the different sleep modes and their wake-up
, while allowing the other clocks to run.
X
X
X
X
X
X
(3)
(3)
(3)
(3)
(3)
“SMCR – Sleep Mode Control Register” on page
X
X
X
X
X
X
X
Wake-up Sources
X
X
X
(2)
X
X
X
X
X
X
X
X
X
X
X
52

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