AT91SAM9XE128-CU Atmel, AT91SAM9XE128-CU Datasheet - Page 839
AT91SAM9XE128-CU
Manufacturer Part Number
AT91SAM9XE128-CU
Description
MCU ARM9 128K FLASH 217-BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE128-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ATMEL
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46.2.3.5
46.2.3.6
46.2.4
46.2.4.1
46.2.5
46.2.5.1
6254C–ATARM–22-Jan-10
Reset Controller (RSTC)
Static Memory Controller (SMC)
MCI: Small Block Reading
MCI: old SDCard Compatibility
RSTC: Reset Type Status is wrong at power-up
SMC: Chip Select Parameters Modification
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the
PDC channel by writing PDC_TXTEN or PDC_RXTEN.
In case of a read of a small block (i.e., 5 bytes) by the READ_SINGLE_BLOCK command
(CMD17), the DATA FSM may not perform correctly. This occurs if the read transfer is done
before the response start bit is sent by the card. It leads to erratic behavior of the NOTBUSY flag
and to a false data time-out error, DTOE.
None.
Busy line is sampled 2 clock cycles after the command End Bit when the R1B response type is
expected. This timing is not strictly defined in SD mode.
This timing is defined with MMC specification 4.1. (R1b Busy Timing)
None.
RSTTYP status in the Reset Controller Status Register is wrong at power-up.
It should be “0” (General Reset) but it is “5” (Brownout Reset). The value is the same if Brownout
and Brownout Reset are enabled or not. The BODSTS bit remains correct.
None.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code
from a memory connected on this CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9XE128/256/512 Preliminary
839
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