LPC2103FHN48H/6,51 NXP Semiconductors, LPC2103FHN48H/6,51 Datasheet - Page 19

• Manufacturer Part Number: LPC2103FHN48H/6,51
• Description: IC ARM7 MCU FLASH 32K 48HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2103FHN48H/6,51

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 70MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC21
• Core: ARM7 TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 70 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DB-LQFP48-LPC2103, MCB2103, MCB2103U, MCB2103UME, KSK-LPC2103-01, KSK-LPC2103-01PL, KSK-LPC2103-02
• Development Tools By Supplier: OM10079, OM10081, OM10090
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288984518

NXP Semiconductors
LPC2101_02_03_4
Product data sheet
CAUTION
6.17.4 Code security (Code Read Protection - CRP)
6.17.5 External interrupt inputs
6.17.6 Memory mapping control
6.17.7 Power control
This feature of the LPC2101/02/03 allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.
Implemented in bootloader code version 2.21 are three levels of the Code Read
Protection:
Remark: Parts LPC2101/02/03 Revision ‘-’ have CRP2 enabled only (bootloader code
version 2.2).
The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processed
as three independent interrupt signals. The external interrupt inputs can optionally be
used to wake-up the processor from Power-down mode and Deep power-down mode.
Additionally all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.
The memory mapping control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down
mode, and Deep power-down mode.
1. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
2. CRP2 disables access to chip via the JTAG and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to chip via
flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors cannot be erased.
update using a reduced set of the ISP commands.
the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART0.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
Rev. 04 — 2 June 2009
Single-chip 16-bit/32-bit microcontrollers
LPC2101/02/03
© NXP B.V. 2009. All rights reserved.
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