Z8F0823PJ005SG Zilog, Z8F0823PJ005SG Datasheet - Page 38

• Manufacturer Part Number: Z8F0823PJ005SG
• Description: IC ENCORE MCU FLASH 8K 28-DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0823PJ005SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 269-4218; Z8F0823PJ005SG

Reset Sources
PS025203-0405
Reset Type
STOP Mode Recovery
STOP Mode Recovery with
Crystal Oscillator Enabled
Table 9. Reset and STOP Mode Recovery Characteristics and Latency (Continued)
During a System Reset or STOP Mode Recovery, the Internal Precision Oscillator requires
4
cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash
option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because
of a low voltage condition or power on reset, this delay is measured from the time that the
supply voltage first exceeds the POR level (discussed later in this chapter). If the external
pin reset remains asserted at the end of the reset period, the device remains in reset until
the pin is deasserted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watch-Dog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses
that value into the Program Counter. Program execution begins at the Reset vector
address.
Because the control registers are re-initialized by a system reset, the system clock after
reset is always the IPO. User software must reconfigure the oscillator control block, such
that the correct system clock source is enabled and selected.
Table 10 lists the possible sources of a system reset.
µ
s to start up. Then the Z8 Encore!
Control Registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
Unaffected, except
WDT_CTL and
OSC_CTL registers
P R E L I M I N A R Y
Reset Characteristics and Latency
®
Reset 66 Internal Precision Oscillator Cycles
Reset 5000 Internal Precision Oscillator Cycles
Z8F0823 Series device is held in Reset for 66
CPU
eZ8
Reset Latency (Delay)
Z8 Encore!
Reset and STOP Mode Recovery
0002H
Product Specification
and
®
Z8F0823 Series
0003H
and loads
21