Z8F0822PJ020SG Zilog, Z8F0822PJ020SG Datasheet - Page 130

IC ENCORE MCU FLASH 8K 28DIP

Z8F0822PJ020SG

Manufacturer Part Number
Z8F0822PJ020SG
Description
IC ENCORE MCU FLASH 8K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheets

Specifications of Z8F0822PJ020SG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Controller Family/series
Z8
No. Of I/o's
19
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
Z8F082xx
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
19
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4208
Z8F0822PJ020SG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F0822PJ020SG
Manufacturer:
Zilog
Quantity:
45
PS022517-0508
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
Transfer Format PHASE is 0
Figure 23
to 0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL
set to one. The diagram can be interpreted as either a Master or Slave timing diagram since
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
Transfer Format PHASE is 1
Figure 24
waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL
set to 1.
MOSI
MISO
SCK
SCK
SS
displays the timing diagram for an SPI transfer in which PHASE is cleared
displays the timing diagram for an SPI transfer in which PHASE is one. Two
Bit7
Bit7
Figure 23. SPI Timing When PHASE is 0
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Z8 Encore! XP
Bit1
Bit1
Product Specification
Serial Peripheral Interface
Bit0
Bit0
®
F0822 Series
117

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