Z8F0822PJ020SG Zilog, Z8F0822PJ020SG Datasheet - Page 131

• Manufacturer Part Number: Z8F0822PJ020SG
• Description: IC ENCORE MCU FLASH 8K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0822PJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Controller Family/series: Z8
• No. Of I/o's: 19
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: Z8F082xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4208; Z8F0822PJ020SG

PS022517-0508
Input Sample Time
Multi-Master Operation
Slave Operation
(CLKPOL = 0)
(CLKPOL = 1)
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
OPEN-DRAIN mode to prevent bus contention. At any one time, only one SPI device is
configured as the Master and all other SPI devices on the bus are configured as Slaves.
The Master enables a single Slave by asserting the SS pin on that Slave only. Then, the
single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the
Slaves (including those which are not enabled). The enabled Slave drives data out its
MISO pin to the MISO Master pin.
For a Master device operating in a multi-master system, if the SS pin is configured as
an input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status
Register. The COL bit indicates the occurrence of a multi-master collision (mode fault
error condition).
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE
Register. The IRQE, PHASE, CLKPOL, and WOR bits in the SPICTL Register and the
MOSI
MISO
SCK
SCK
SS
Bit7
Bit7
Figure 24. SPI Timing When PHASE is 1
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Z8 Encore! XP
Bit2
Bit2
Product Specification
Serial Peripheral Interface
Bit1
Bit1
®
F0822 Series
Bit0
Bit0
118