Z8F0822PJ020SG Zilog, Z8F0822PJ020SG Datasheet - Page 98

• Manufacturer Part Number: Z8F0822PJ020SG
• Description: IC ENCORE MCU FLASH 8K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0822PJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Controller Family/series: Z8
• No. Of I/o's: 19
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: Z8F082xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4208; Z8F0822PJ020SG

PS022517-0508
Watchdog Timer Reload Unlock Sequence
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the WDT forces the device into
the Reset state. The WDT status bit in the WDT Control Register is set to 1. For more infor-
mation on Reset, see
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs
and the device is in STOP mode, the WDT initiates a Stop Mode Recovery. Both the
WDT status bit and the STOP bit in the WDT Control Register is set to 1 following
WDT time-out in STOP mode. For more information on Reset, see
Recovery
during STOP mode.
WDT RC Disable in STOP Mode
To minimize power consumption in STOP mode, the WDT and its RC oscillator can be
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the Z8F082x family device enters STOP mode following execution of a
1. Write
2. Write
3. Write
Writing the unlock sequence to the WDTCTL address unlocks the three Watchdog Timer
Reload Byte Registers (WDTU, WDTH, and WDTL) to allow changes to the time-out
period. These write operations to the WDTCTL address produce no effect on the bits in
the WDTCTL. The locking mechanism prevents spurious writes to the Reload Registers.
The following sequence is required to unlock the Watchdog Timer Reload Byte Registers
(WDTU, WDTH, and WDTL) for write access.
1. Write
2. Write
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
and its oscillator to be disabled during STOP mode. Alternatively, write
Watchdog Timer Control Register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during STOP mode. This
sequence only affects WDT operation in STOP mode.
on page 39. Default operation is for the WDT and its RC oscillator to be enabled
81H
55H
AAH
55H
AAH
to the Watchdog Timer Control Register (WDTCTL) to configure the WDT
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
Reset and Stop Mode Recovery
on page 39.
Z8 Encore! XP
Product Specification
Reset and Stop Mode
STOP
®
F0822 Series
Watchdog Timer
00H
instruction:
to the
85