Z8F2422AR020SG Zilog, Z8F2422AR020SG Datasheet - Page 167
Z8F2422AR020SG
Manufacturer Part Number
Z8F2422AR020SG
Description
IC ENCORE MCU FLASH 24K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F2422AR020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F242x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4251
Z8F2422AR020SG
Z8F2422AR020SG
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Table 70. I
Table 71. I
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
I
2
C Status Register
2
2
C Data Register (I2CDATA)
C Status Register (I2CSTAT)
TDRE
7
7
1
The Read-only I
TDRE—Transmit Data Register Empty
When the I
When this bit is set, an interrupt is generated if the TXI bit is set, except when the I
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit is cleared by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
This bit is cleared by reading the I
cution of the On-Chip Debugger’s Read Register command).
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or
received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
last byte transmitted or received. It is not reset at the beginning of each transaction and is
not reset when this register is read.
RDRF
2
6
6
C Controller is enabled, this bit is 1 when the I
2
C Status register
ACK
5
5
2
C Controller is enabled and the I
2
10B
(Table
C Data register (unless the read is performed using exe-
4
4
DATA
F50H
F51H
R/W
R
71) indicates the status of the I
0
RD
3
3
0
2
C Controller to generate an interrupt.
Z8 Encore! XP
TAS
2
2
2
C Data register is empty.
2
C Controller has received a
Product Specification
DSS
1
1
®
2
C Controller.
F64XX Series
I2C Controller
NCKI
2
0
0
C
153
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