Z8F2422AR020SG Zilog, Z8F2422AR020SG Datasheet - Page 176
Z8F2422AR020SG
Manufacturer Part Number
Z8F2422AR020SG
Description
IC ENCORE MCU FLASH 24K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F2422AR020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F242x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4251
Z8F2422AR020SG
Z8F2422AR020SG
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PS019921-0308
DMA_ADC Operation
Configuring DMA_ADC for Data Transfer
3. Write the Start and End Register File address high nibbles to the DMAx End/Start
4. Write the lower byte of the Start Address to the DMAx Start/Current Address register.
5. Write the lower byte of the End Address to the DMAx End Address register.
6. Write to the DMAx Control register to complete the following:
DMA_ADC transfers data from the ADC to the Register File. The sequence of operations
in a DMA_ADC data transfer is:
1. ADC completes conversion on the current ADC input channel and signals the DMA
2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte
4. If the current ADC Analog Input is the highest numbered input to be converted:
Follow the steps below to configure and enable DMA_ADC:
1. Write the DMA_ADC Address register with the 7 most-significant bits of the Register
2. Write to the DMA_ADC Control register to complete the following:
Address High Nibble register.
–
–
–
–
–
–
controller that two-bytes of ADC data are ready for transfer.
ADC output value to the Register File and then returns system bus control back to the
eZ8 CPU.
–
–
If the current ADC Analog Input is not the highest numbered input to be converted,
DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input.
File address for data transfers.
Select loop or single-pass mode operation
Select the data transfer direction (either from the Register File RAM to the on-
chip peripheral control register; or from the on-chip peripheral control register to
the Register File RAM)
Enable the DMAx interrupt request, if desired
Select Word or Byte mode
Select the DMAx request trigger
Enable the DMAx channel
DMA_ADC resets the ADC Analog Input number to 0 and initiates data
conversion on ADC Analog Input 0.
If configured to generate an interrupt, DMA_ADC sends an interrupt request to
the Interrupt Controller
Z8 Encore! XP
Direct Memory Access Controller
Product Specification
®
F64XX Series
162
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