ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 50

IC MCU 8BIT 16K FLASH 44-LQFP

ST72F561J4T6

Manufacturer Part Number
ST72F561J4T6
Description
IC MCU 8BIT 16K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F561J4T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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0
ST72561
I/O PORTS (Cont’d)
9.6 I/O PORT REGISTER CONFIGURATIONS
The I/O port register configurations are summa-
rized as follows.
9.6.1 Standard Ports
PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0,
PF7:0
9.6.2 Interrupt Ports
PA0,2,4,6; PB0,2,4; PC1; PD0,6
(with pull-up)
50/265
floating input
pull-up input
open drain output
push-pull output
floating input
pull-up interrupt input
open drain output
push-pull output
MODE
MODE
DDR
DDR
0
0
1
1
0
0
1
1
OR
OR
0
1
0
1
0
1
0
1
PA1,3,5,7; PB1,3,5; PC2; PD1,4,7
(without pull-up)
9.6.3 Pull-up Input Port (CANTX requirement)
PC4
The PC4 port cannot operate as a general pur-
pose output. The CAN peripheral controls it direct-
ly when enabled. Otherwise, PC4 is a pull-up in-
put.
If DDR = 1 it is still possible to read the port
through the DR register.
floating input
floating interrupt input
open drain output
push-pull output
MODE
pull-up input
MODE
DDR
0
0
1
1
OR
0
1
0
1

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