ST72F63BK4M1 STMicroelectronics, ST72F63BK4M1 Datasheet - Page 120

• Manufacturer Part Number: ST72F63BK4M1
• Description: IC MCU 8BIT LS 16K 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BK4M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• For Use With: 497-5521 - EVAL BOARD LOW SPEED USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-2115-5

On-chip peripherals
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3 BTF Byte transfer finished.
2 ADSL Address matched (Slave mode). This bit is set by hardware as soon as the
1 M/SL Master/Slave.
0 SB Start bit (Master mode).
This bit is set by hardware as soon as a byte is correctly received or transmitted
with interrupt generation if ITE=1. It is cleared by software reading SR1 register
followed by a read or write of DR register. It is also cleared by hardware when the
interface is disabled (PE=0).
Following a byte transmission, this bit is set after reception of the acknowledge
clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See
byte in DR register.
Following a byte reception, this bit is set after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading
the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
received slave address matched with the OAR register content or a general call is
recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1
register or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled
(PE=0).
0: Slave mode
1: Master mode
This bit is set by hardware as soon as the Start condition is generated (following a
write START=1). An interrupt is generated if ITE=1. It is cleared by software reading
SR1 register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
Figure
48). BTF is cleared by reading SR1 register followed by writing the next
Doc ID 7516 Rev 8
ST7263Bxx