Z8F6421AN020EC00TR Zilog, Z8F6421AN020EC00TR Datasheet - Page 166

• Manufacturer Part Number: Z8F6421AN020EC00TR
• Description: IC ENCORE MCU FLASH 64K 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F6421AN020EC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• For Use With: 269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6421AN020EC00T

I
PS019921-0308
2
C Control Register Definitions
I
2
C Data Register
15. The I
16. The I
17. The I
18. The I
19. The I
20. The I
21. Software responds by reading the I
22. If there are one or more bytes to transfer, return to
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I
24. Software responds by setting the STOP bit of the I
25. A STOP condition is sent to the I
The I
the I
from the I
sible in the Register File address space, but is used only to buffer incoming and outgoing
data.
register (third address transfer).
slave read address and a 1 (read).
high period of SCL
If the slave were to Not Acknowledge at this point (this should not happen because the
slave did acknowledge the first two address bytes), software would respond by setting
the STOP and FLUSH bits and clearing the TXI bit. The I
STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
I
byte), else it sends an Acknowledge.
is only one more byte to receive, set the NAK bit of the I
Controller.
2
2
2
C Shift register during a write to a slave. This register also holds data that is loaded
C Controller sends a Not Acknowledge to the I
C Data register (see
2
2
2
2
2
2
2
C Controller sends the repeated START condition.
C Controller loads the I
C Controller sends
C slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller shifts in a byte of data from the I
C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
C Shift register during a read from a slave. The I
Table 70
11110B
2
C Shift register with the contents of the I
on page 153) holds the data that is to be loaded into
2
C slave and the STOP and NCKI bits are cleared.
2
followed by the two most significant bits of the
C Data register which clears the RDRF bit. If there
2
C slave if the NAK bit is set (last
2
step
Z8 Encore! XP
C Control register.
2
C slave on the SDA signal. The
19.
2
C Shift Register is not acces-
2
C Control register.
2
C Controller sends the
Product Specification
®
F64XX Series
2
C Data
I2C Controller
2
C
152