ST10R172LT1 STMicroelectronics, ST10R172LT1 Datasheet - Page 28

• Manufacturer Part Number: ST10R172LT1
• Description: MCU 16BIT ROMLESS LV 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R172LT1

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: ST10
• No. Of I/o's: 77
• Ram Memory Size: 1KB
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Embedded Interface Type: SPI, USART
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition

ST10R172L - SPECIAL FUNCTION REGISTERS
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Name
MDH
MDL
ODP2
ODP3
ODP6
ODP7
ONES
P0L
P0H
P1L
P1H
P2
P3
P4
P5
P6
P7
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PP3
b
b
b
b
b
b
b
b
b
b
b
b
b
b
Physical
Address
FE0Ch
FE0Eh
F1C2h
F1C6h
F1CEh
F1D2h
FF1Eh
FF00h
FF02h
FF04h
FF06h
FFC0h
FFC4h
FFC8h
FFA2h
FFCCh
FFD0h
FEC0h
FEC2h
FEC4h
FEC6h
FEC8h
FECAh
FECCh
FECEh
F03Eh
E
E
E
E
E
Table 10 Special functional registers
8-Bit
Address
06h
07h
E1h
E3h
E7h
E9h
8Fh
80h
81h
82h
83h
E0h
E2h
E4h
D1h
E6h
E8h
60h
61h
62h
63h
64h
65h
66h
67h
1Fh
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
Description
CPU Multiply Divide Register – High Word
CPU Multiply Divide Register – Low Word
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Constant Value 1’s Register (read only)
Port 0 Low Register (Lower half of PORT0)
Port 0 High Register (Upper half of PORT0)
Port 1 Low Register (Lower half of PORT1)
Port 1 High Register (Upper half of PORT1)
Port 2 Register (4 bits)
Port 3 Register
Port 4 Register (8 bits)
Port 5 Register (read only)
Port 6 Register (8 bits)
Port 7Register (4 bits)
PWM Module Period Register 3
Reset
Value
0000h
0000h
-0--h
0000h
00h
-0h
FFFFh
00h
00h
00h
00h
-0--h
0000h
00h
XXXXh
00h
-0h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h