ST72C334J2T6 STMicroelectronics, ST72C334J2T6 Datasheet - Page 35
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ST72C334J2T6
Manufacturer Part Number
ST72C334J2T6
Description
MCU 8BIT FLASH SPI SCI 44TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72C124J2T6.pdf
(153 pages)
Specifications of ST72C334J2T6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ST72C3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7C334-INDART, ST7MDT2-EPB2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4837
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72C334J2T6
Manufacturer:
analogic
Quantity:
3 188
Company:
Part Number:
ST72C334J2T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
11 POWER SAVING MODES
11.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see
TIVE HALT and HALT.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 19. Power Saving Mode Transitions
Figure
19): SLOW, WAIT (SLOW WAIT), AC-
ACTIVE HALT
SLOW WAIT
POWER CONSUMPTION
SLOW
HALT
WAIT
RUN
Low
High
CPU
).
11.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
– To adapt the internal clock frequency (f
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 20. SLOW Mode Clock Transitions
internal clock in the device,
the available supply voltage.
ST72334J/N, ST72314J/N, ST72124J
CP1:0
f
SMS
f
OSC
CPU
/2
FREQUENCY
00
f
NEW SLOW
OSC
REQUEST
/4
01
CPU
f
OSC
NORMAL RUN MODE
).
/8
REQUEST
CPU
f
OSC
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) to
/2