ST72C334J2T6 STMicroelectronics, ST72C334J2T6 Datasheet - Page 94
![MCU 8BIT FLASH SPI SCI 44TQFP](/photos/6/84/68458/497-44-tqfp_44-lqfp_sml.jpg)
ST72C334J2T6
Manufacturer Part Number
ST72C334J2T6
Description
MCU 8BIT FLASH SPI SCI 44TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72C124J2T6.pdf
(153 pages)
Specifications of ST72C334J2T6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ST72C3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7C334-INDART, ST7MDT2-EPB2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4837
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72C334J2T6
Manufacturer:
analogic
Quantity:
3 188
Company:
Part Number:
ST72C334J2T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: Undefined
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Address Mark
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00 h)
Bit 7 = TIE Transmitter interrupt enable .
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: interrupt is inhibited
94/153
TIE
R8
TDRE=1 in the SR register.
7
7
TCIE
T8
RIE
-
ILIE
M
WAKE
TE
RE
-
RWU
-
SBK
0
0
-
1: An SCI interrupt is generated whenever TC=1 in
Bit 5 = RIE Receiver interrupt enable .
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled.
1: Receiver is enabled and begins searching for a
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
the SR register
or RDRF=1 in the SR register
in the SR register.
the I/O port configuration.
start bit.