Z16F2810FI20EG Zilog, Z16F2810FI20EG Datasheet - Page 207

• Manufacturer Part Number: Z16F2810FI20EG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810FI20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-BQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ESPI Control Register Definitions
PS022008-0810
ESPI Baud Rate Generator
ESPI Data Register
SPI BRG Interrupt Interval (s)
TUND, COL, ABT, ROVR —See the Status register for description of these bits.
RSS—Value of SS associated with last byte written (useful in I2S mode to distinquish 
left/right channel data).
In ESPI MASTER mode, the BRG creates a lower frequency serial clock (SCK) for data
transmission synchronization between the Master and the external Slave. The input to the
BRG is the system clock. The ESPI Baud Rate High and Low Byte registers combine to
form a 16-bit reload value, BRG[15:0], for the ESPI BRG. The ESPI baud rate is
calculated using the following equation:
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 x 65536 = 131072).
When the ESPI is disabled, the BRG functions as a basic 16-bit timer with interrupt on
timeout. Follow the steps below to configure the BRG as a timer with interrupt on timeout:
1. Disable the ESPI by clearing the ESPIEN1,0 bits in the ESPI Control register.
2. Load the appropriate 16-bit count value into the ESPI Baud Rate High and Low Byte
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
The ESPI Data register (see
and the incoming Receive Data register. Reads from the ESPI Data register return the
contents of the Receive Data register. The Receive Data register is updated with the
contents of the shift register at the end of each transfer. Writes to the ESPI Data register
SPI Baud Rate (bps)
registers.
the ESPI Control register to 1.
Table 97. ESPI Rx DMA Descriptor Status field
0
=
P R E L I M I N A R Y
RSS
Table
System Clock Frequency (Hz)
--------------------------------------------------------------------------- -
98) addresses both the outgoing Transmit Data register
=
2 BRG[15:0]

System Clock Period (s) BRG[15:0]
ABT
Enhanced Serial Peripheral Interface
ROVR
Product Specification
ZNEO

Z16F Series
191