W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 19
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W77E058A40DL
Manufacturer Part Number
W77E058A40DL
Description
IC MCU 8-BIT 32K FLASH 40-DIP
Manufacturer
Nuvoton Technology Corporation of America
Series
W77r
Specifications of W77E058A40DL
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, Serial Port
Peripherals
POR, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP
Cpu Family
W77
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
UART
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
40
Package Type
PDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W77E058A40DL
Manufacturer:
WINBOND
Quantity:
4 500
Company:
Part Number:
W77E058A40DL
Manufacturer:
WINBOND
Quantity:
5
Part Number:
W77E058A40DL
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Poot 2
P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper
Port 4
P4.3-0: Port 4 is a bi-directional I/O port with internal pull-ups. Port 4 can not use bit-addressable
Interrupt Enable
EA:
ES1:
ET2:
ES:
ET1:
EX1:
ET0:
EX0:
Slave Address
SADDR: The SADDR should be programmed to the given or broadcast address for serial port 0 to
address bits for accesses to external memory.
instruction (SETB or CLR).
Global enable. Enable/disable all interrupts.
Enable Serial Port 1 interrupt.
Enable Timer 2 interrupt.
Enable Serial Port 0 interrupt.
Enable Timer 1 interrupt
Enable external interrupt 1
Enable Timer 0 interrupt
Enable external interrupt 0
which the slave processor is designated.
Mnemonic: P2
Mnemonic: P4
Mnemonic: IE
Mnemonic: SADDR
Bit:
Bit:
Bit:
Bit:
P2.7
EA
7
7
7
7
-
P2.6
ES1
6
6
6
6
-
P2.5
ET2
- 19 -
5
5
5
5
-
P2.4
ES
4
4
4
4
-
Publication Release Date: April 17, 2007
P4.3
P2.3
ET1
3
3
3
3
Address: A0h
Address: A5h
Address: A8h
Address: A9h
P2.2
P4.2
EX1
2
2
2
2
W77E058A
P2.1
P4.1
ET0
1
1
1
1
Revision A10
P2.0
P4.0
EX0
0
0
0
0