W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 72

• Manufacturer Part Number: W77E058A40DL
• Description: IC MCU 8-BIT 32K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40DL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

W77E058A
16. ON-CHIP FLASH EPROM CHARACTERISTICS
The W77E058 has several modes to program the on-chip Flash EPROM. All these operations are
configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
( EA ). Moreover, the A15−A0(P2.7−P2.0,
OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and V
PP
P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these
operations.
Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
Output Disable Condition
When the OE is set to high, no data output appears on the D7..D0.
Program Operation
This operation is used to program the data to Flash EPROM and the security bits. Program operation
is done when the V
is reach to V
(12.5V) level, CE set to low, and OE set to high.
PP
CP
Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the Flash
EPROM cells and the security bits from 0 to 1. This erase operation is done when the V
is reach to
PP
V
level, CE set to low, and OE set to high.
EP
Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if V
= V
(14.5V), CE is high and OE
PP
EP
is low.
Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6( CE ) = V
, P3.7( OE ) = V
, erasing or programming of non-targeted chips is inhibited. So,
IH
IH
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
- 72 -