STM32F105R8T6 STMicroelectronics, STM32F105R8T6 Datasheet - Page 30

MCU ARM 64KB FLASH MEM 64-LQFP

STM32F105R8T6

Manufacturer Part Number
STM32F105R8T6
Description
MCU ARM 64KB FLASH MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheets

Specifications of STM32F105R8T6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
51
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
STM32F105x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
20 KB
Interface Type
CAN, I2C, SPI, USART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
51
Number Of Timers
10
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit x 2, 16 Channel
On-chip Dac
12 bit x 2, 2 Channel
Cpu Family
STM32
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
20KB
# I/os (max)
51
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
For Use With
497-10591 - DAUGHTER BOARD FOR STM32497-9040 - DEV KIT FOR STM32497-9041 - DEV KIT FOR STM32497-9042 - DEV KIT FOR STM32497-9043 - DEV KIT FOR STM32497-8924 - EVAL BOARD FOR STM32F107VCT497-8853 - BOARD DEMO STM32 UNIV USB-UUSCI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-8922

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Pinouts and pin description
Table 5.
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT = 5 V tolerant. All I/Os are V
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
8. SPI2/I2S2 and I2C2 are not available when the Ethernet is being used.
9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
30/101
A7 55 89
A6 56 90
C5 57 91
B5 58 92
A5 59 93
D5 60 94
B4 61 95
A4 62 96
D4
C4
E5 63 99
F5 64 100
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and BGA100 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual.
Pins
-
-
97
98
Pin definitions (continued)
Pin name
BOOT0
V
V
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
DD
I/O FT
I/O FT
I/O
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
I
capable.
(after reset)
function
NJTRST
BOOT0
V
JTDO
V
Main
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
Doc ID 15274 Rev 5
(3)
ETH_MII_PPS_OUT / I2S3_SD
TIM4_CH3
I2C1_SMBA / SPI3_MOSI /
I2C1_SCL
I2C1_SDA
ETH_RMII_PPS_OUT
SPI3_SCK / I2S3_CK
TIM4_CH4
SPI3_MISO
TIM4_ETR
(7)
Default
(7)
(7)
/ ETH_MII_TXD3
/TIM4_CH1
/TIM4_CH2
Alternate functions
(7)
STM32F105xx, STM32F107xx
(7)
(7)
TIM3_CH2/SPI1_MOSI/
USART1_TX/CAN2_TX
TIM2_CH2 / SPI1_SCK
I2C1_SDA / CAN1_TX
I2C1_SCL/CAN1_RX
PB3 / TRACESWO/
PB4 / TIM3_CH1/
(4)
USART1_RX
SPI1_MISO
CAN2_RX
Remap

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