ST10F269Z2T3 STMicroelectronics, ST10F269Z2T3 Datasheet - Page 122

• Manufacturer Part Number: ST10F269Z2T3
• Description: MCU 16BIT 256KBIT FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19 - POWER REDUCTION MODES
19 - POWER REDUCTION MODES
Two different power reduction modes with different
levels of power reduction have been implemented
in the ST10F269. In Idle mode only CPU is
stopped, while peripheral still operate. In Power
Down mode both CPU and peripherals are
stopped.
Both mode are software activated by a protected
instruction and are terminated in different ways as
described in the following sections.
Note:
19.1 - Idle Mode
Idle mode is entered by running IDLE protected
instruction. The CPU operation is stopped and the
peripherals still run.
Idle mode is terminate by any interrupt request.
Whatever the interrupt is serviced or not, the
instruction following the IDLE instruction will be
executed after return from interrupt (RETI)
instruction, then the CPU resumes the normal
program.
Note that a PEC transfer keep the CPU in Idle
mode. If the PEC transfer does not succeed, the
Idle mode is terminated. Watchdog timer must be
properly programmed to avoid any disturbance
during Idle mode.
19.2 - Power Down Mode
Power Down mode starts by running PWRDN
protected instruction. Internal clock is stopped, all
MCU parts are on hold including the watchdog
timer.
There are two different operating Power Down
modes: protected mode and interruptible mode.
The internal RAM contents can be preserved
EXICON (F1C0h / E0h
122/184
EXIxES(x=7...0)
15
EXI7ES
RW
All external bus actions are completed
before Idle or Power Down mode is
entered. However, Idle or Power Down
mode is not entered if READY is enabled,
but has not been activated (driven low for
negative polarity, or driven high for
positive polarity) during the last bus
access.
14
13
EXI6ES
RW
12
External Interrupt x Edge Selection Field (x=7...0)
0 0:
Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
11
EXI5ES
RW
10
9
EXI4ES
RW
8
ESFR
through the voltage supplied via the V
verify RAM integrity, some dedicated patterns
may be written before entering the Power Down
mode and have to be checked after Power Down
is resumed.
It is mandatory to keep V
power-down mode, because
voltage regulator is turned in power saving
mode and it delivers 2.5V to the core logic, but
it must be supplied at nominal V
19.2.1 - Protected Power Down Mode
This mode is selected when PWDCFG (bit 5) of
SYSCON register is cleared. The Protected
Power Down mode is only activated if the NMI pin
is pulled low when executing PWRDN instruction
(this means that the PWRD instruction belongs to
the NMI software routine). This mode is only
deactivated with an external hardware reset on
RSTIN pin.
Note: During power down the on-chip voltage
19.2.2 - Interruptible Power Down Mode
This mode is selected when PWDCFG (bit 5) of
SYSCON register is set (See Chapter : Special
Function Register Overview on page 125).
The Interruptible Power Down mode is only
activated if all the enabled Fast External Interrupt
pins are in their inactive level (see EXICON
register description below).
This mode is deactivated with an external reset
applied to RSTIN pin or with an interrupt request
applied to one of the Fast External Interrupt pins.
To allow the internal PLL and clock to stabilize,
the RSTIN pin must be held low according
the recommendations
System Reset on page 114.
7
EXI3ES
RW
6
regulator automatically lowers the internal
logic supply voltage to 2.5V, to save power
and to keep internal RAM and registers
contents.
5
EXI2ES
RW
4
described
3
DD
EXI1ES
RW
= +5V ±10% during
Reset Value: 0000h
2
DD
the
in
ST10F269
= +5V.
DD
1
EXI0ES
Chapter :
RW
on-chip
pins. To
0