ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 28

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST10F168
10 - GENERAL PURPOSE TIMER UNIT
The GPT unit is a flexible multifunctional timer /
counter structure which is used for time related
tasks such as event timing and counting, pulse
width and duty cycle measurements, pulse
generation, or pulse multiplication. The GPT unit
contains five 16-bit timers organized into two
separate modules GPT1 and GPT2. Each timer
in each module may operate independently in
several different modes, or may be concatenated
with another timer of the same module.
10.1 - GPT1
Each of the three timers T2, T3, T4 of the GPT1
module can be configured individually for one of
four basic modes of operation: timer, gated
timer, counter mode and incremental interface
mode. In timer mode, the input clock for a timer is
derived from the CPU clock, divided by a pro-
grammable prescaler. In counter mode, the timer is
clocked in reference to external events. Pulse width
or duty cycle measurement is supported in gated
timer mode where the operation of a timer is con-
trolled by the ‘gate’ level on an external input pin.
For these purposes, each timer has one associated
port pin (TxIN) which serves as gate or clock input.
Table 14 lists the timer input frequencies, resolu-
tion and periods for each pre-scaler option at
25MHz CPU clock. This also applies to the Gated
Timer Mode of T3 and to the auxiliary timers T2
and T4 in Timer and Gated Timer Mode.
The count direction (up / down) for each timer is
programmable by software or may be altered
dynamically by an external signal on a port pin
(TxEUD).
In Incremental Interface Mode, the GPT1 timers
(T2, T3, T4) can be connected directly to the
incremental position sensor signals A and B by
their respective inputs TxIN and TxEUD. Direction
and count signals are internally derived from
these two input signals so that the contents of the
Table 14 : GPT1 timer input frequencies, resolution and periods
28/74
Pre-scaler Factor
Input Frequency
Resolution
Period
f
CPU
= 25MHz
3.125MHz 1.563MHz 781.3MHz
21.0ms
320ns
000b
8
41.9ms
640ns
001b
16
83.9ms
1.28 s
010b
32
Timer Input Selection T2I / T3I / T4I
390KHz
2.56 s
167ms
011b
respective timer Tx corresponds to the sensor
position. The third position sensor signal TOP0
can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which
changes state on each timer over-flow / under-
flow. The state of this latch may be output on port
pins (TxOUT) e. g. for time out monitoring of
external hardware components, or may be used
internally to clock timers T2 and T4 for high reso-
lution of long duration measurements.
In addition to their basic operating modes, timers
T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or
reload registers, timers T2 and T4 are stopped.
The contents of timer T3 is captured into T2 or T4
in response to a signal at their associated input
pins (TxIN). Timer T3 is reloaded with the
contents of T2 or T4 triggered either by an
external signal or by a selectable state transition
of its toggle latch T3OTL. When both T2 and T4
are configured to alternately reload T3 on
opposite state transitions of T3OTL with the low
and high times of a PWM signal, this signal
can be constantly generated without software
intervention.
10.2 - GPT2
The GPT2 module provides precise event control
and time measurement. It includes two timers (T5,
T6) and a capture / reload register (CAPREL).
Both timers can be clocked with an input clock
which is derived from the CPU clock via a pro-
grammable prescaler or with external signals. The
count direction (up / down) for each timer is pro-
grammable by software or may additionally be
altered dynamically by an external signal on a port
pin (TxEUD). Concatenation of the timers is sup-
ported via the output toggle latch (T6OTL) of timer
T6 which changes its state on each timer
overflow / underflow.
64
195.3KHz 97.66KHz
5.12 s
336ms
100b
128
10.24 s
671ms
101b
256
48.83KHz 24.41KHz
20.48 s
1.34s
110b
512
40.96 s
2.68s
111b
1024