ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 57

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ST10F168SQ6

Manufacturer Part Number
ST10F168SQ6
Description
MCU 256KB FLASH 12K RAM 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheets

Specifications of ST10F168SQ6

Core Processor
ST10
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-MQFP, 144-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST10F168SQ6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F168SQ6 ST10F168-Q3
Manufacturer:
ST
0
20.5.9 - Memory Cycle Variables
The tables below use three variables which are derived from the BUSCONx registers and which
represent the special characteristics of the programmed memory cycle. The following table describes
how these variables are computed.
20.5.10 - Multiplexed Bus
V
ALE cycle time = 6 TCL + 2t
specified.
Table 24 : Multiplexed bus characteristics
t
t
t
t
t
t
t
t
t
t
t
Symbol
DD
t
t
t
t
t
10
11
12
13
14
15
16
17
18
19
22
5
6
7
8
9
Symbol
= 5V 10%, V
t
t
t
A
C
F
CC ALE high time
CC Address setup to ALE
CC Address hold after ALE
CC ALE falling edge to RD, WR
CC ALE falling edge to RD, WR
CC Address float after RD, WR
CC Address float after RD, WR
CC RD, WR low time (with RW-delay)
CC RD, WR low time (no RW-delay)
SR RD to valid data in (with RW-delay)
SR RD to valid data in (no RW-delay)
SR ALE low to valid data in
SR Address / Unlatched CS to valid
SR Data hold after RD rising edge
SR Data float after RD
CC Data valid to WR
(with RW-delay)
(no RW-delay)
(with RW-delay)
(no RW-delay)
data in
ALE Extension
Memory Cycle Time wait states
Memory Tristate Time
SS
= 0V, for Q6 version : T
Parameter
1
A
+ t
C
1
1
+ t
F
(120ns at 25MHz CPU clock without wait states), unless otherwise
Description
A
Minimum
= -40, +85 C and for Q3 version T
-10 + t
10 + t
10 + t
10 + t
30 + t
50 + t
20 + t
Maximum CPU Clock
4 + t
0
A
A
A
A
C
C
C
A
25MHz
50 + 2t
40 + t
Maximum
20 + t
40 + t
26 + t
26
6
A
A
+ t
C
C
F
+ t
C
C
2TCL - 10 + t
3TCL - 10 + t
2TCL - 20 + t
TCL - 10 + t
TCL - 10 + t
TCL - 10 + t
TCL - 16+ t
Minimum
-10 + t
1/2 TCL = 1 to 25MHz
Variable CPU Clock
0
A
= -40, + 125 C, C
A
A
A
A
A
C
C
C
2TCL x (15 - <MCTC>)
2TCL x (1 - <MTTC>)
TCL x <ALECTL>
2TCL - 14 + t
2TCL - 20+ t
3TCL - 20+ t
Maximum
3TCL - 20
4TCL - 30
+ 2t
+ t
TCL + 6
Values
A
A
6
+ t
+ t
ST10F168
C
C
L
= 100pF,
C
C
F
57/74
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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