ST10F168SQ6 STMicroelectronics, ST10F168SQ6 Datasheet - Page 55

• Manufacturer Part Number: ST10F168SQ6
• Description: MCU 256KB FLASH 12K RAM 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F168SQ6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-MQFP, 144-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.5.4 - Prescaler Operation
When pins P0.15-13 (P0H.7-5) equal ’001’ during
reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
f
duration of an individual TCL) is defined by the
period of the input clock f
The timings listed in the AC Characteristics that
refer to TCL therefore can be calculated using the
period of f
Note that if the bit OWDDIS in SYSCON register
is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
20.5.5 - Direct Drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during
reset the on-chip phase locked loop is disabled and
the CPU clock is directly driven from the internal
oscillator with the input clock signal.
The frequency of f
frequency of f
(i.e. the duration of an individual TCL) is defined
by the duty cycle of the input clock f
Therefore, the timings given in this chapter refer to
the minimum TCL. This minimum value can be
calculated by the following formula:
For two consecutive TCLs, the deviation caused
by the duty cycle of f
duration of 2TCL is always 1/f
value TCL
that require an odd number of TCLs (1,3,...).
Timings that require an even number of TCLs
(2,4,...) may use the formula:
Note:
If bit OWDDIS in the SYSCON register is cleared,
the PLL runs on its free-running frequency and
delivers the clock signal for the Oscillator
Watchdog. If bit OWDDIS is set, then the PLL is
switched off.
XTAL
and the high and low time of f
The address float timings in Multiplexed
bus mode (t
duration of TCL (TCL
DC
TCL mi n
XTAL
min
max
XTAL
has to be used only once for timings
DC
) instead of TCL
for any TCL.
2TCL
=
=
so the high and low time of f
CPU
11
duty cycle
1 f XT AL
XTAL
=
CPU
and t
1 f XTAL
is half the frequency of
XTAL
is compensated, so the
45
directly follows the
.
) use the maximum
XTAL
min
max
DC min
.
. The minimum
XTAL
CPU
= 1/f
.
(i.e. the
XTAL
CPU
x
20.5.6 - Oscillator Watchdog (OWD)
When the clock option selected is direct drive or
direct drive with prescaler, in order to provide a fail
safe mechanism in case of a loss of the external
clock, an oscillator watchdog is implemented as
an additional functionality of the PLL circuitry. This
oscillator watchdog operates as follows :
After a reset, the Oscillator Watchdog is enabled
by default. To disable the OWD, the bit OWDDIS
(bit 4 of SYSCON register) must be set.
When the OWD is enabled, the PLL runs on its
free-running frequency, and increments the
Oscillator Watchdog counter. On each transition
of XTAL1 pin, the Oscillator Watchdog is cleared.
If an external clock failure occurs, then the
Oscillator Watchdog counter overflows (after 16
PLL clock cycles). The CPU clock signal will be
switched to the PLL free-running clock signal, and
the
(XP3INT) is flagged. The CPU clock will not switch
back to the external clock even if a valid external
clock exits on XTAL1 pin. Only a hardware reset
can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is
always fed from the oscillator input and the PLL is
switched off to decrease power supply current.
20.5.7 - Phase Locked Loop
For all other combinations of pins P0.15-13
(P0H.7-5) during reset the on-chip phase locked
loop is enabled and provides the CPU clock (see
Table 23).
The PLL multiplies the input frequency by the
factor F which is selected via the combination of
pins P0.15-13 (i.e. f
F’th
synchronizes the CPU clock to the input clock.
This synchronization is done smoothly, i.e. the
CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the
frequency of f
locked to f
of f
individual TCL.
The timings listed in the AC Characteristics that
refer to TCL therefore must be calculated using
the minimum TCL that is possible under the
respective circumstances.
CPU
Oscillator
transition
which also effects the duration of
XTAL
CPU
. The slight variation causes a jitter
Watchdog
of
is constantly adjusted so it is
CPU
f
XTAL
= f
XTAL
Interrupt
the
x F). With every
PLL
ST10F168
Request
circuit
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