MC9S08QG8MFQE Freescale Semiconductor, MC9S08QG8MFQE Datasheet - Page 264

• Manufacturer Part Number: MC9S08QG8MFQE
• Description: IC MCU 8K FLASH 8-DFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG8MFQE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Development Support
17.4.3.8
This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired
to 0s.
17.4.3.9
This is a read-only status register.
262
Reset
TRG[3:0]
TRGSEL
BEGIN
Field
3:0
W
7
6
R
TRGSEL
Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode
tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate
through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match
address is actually executed.
0 Trigger on access to compare address (force)
1 Trigger if opcode at compare address is executed (tag)
Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until
a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are
assumed to be begin traces.
0 Data stored in FIFO until trigger (end trace)
1 Trigger initiates data storage (begin trace)
Select Trigger Mode — Selects one of nine triggering modes, as described below.
0000 A-only
0001 A OR B
0010 A Then B
0011 Event-only B (store data)
0100 A then event-only B (store data)
0101 A AND B data (full mode)
0110 A AND NOT B data (full mode)
0111 Inside range: A ≤ address ≤ B
1000 Outside range: address < A or address > B
1001 – 1111 (No trigger)
0
7
Debug Trigger Register (DBGT)
Debug Status Register (DBGS)
= Unimplemented or Reserved
BEGIN
0
6
Table 17-5. DBGT Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 17-8. Debug Trigger Register (DBGT)
0
0
5
0
0
4
Description
TRG3
0
3
TRG2
2
0
Freescale Semiconductor
TRG1
0
1
TRG0
0
0