MC9S08QG84CFFER Freescale Semiconductor, MC9S08QG84CFFER Datasheet - Page 261

IC MCU 8BIT 8K FLASH 16-QFN

MC9S08QG84CFFER

Manufacturer Part Number
MC9S08QG84CFFER
Description
IC MCU 8BIT 8K FLASH 16-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08QG84CFFER

Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Data Ram Size
512 B
On-chip Adc
Yes
Number Of Programmable I/os
12
Number Of Timers
1
Mounting Style
SMD/SMT
Height
1 mm
Interface Type
I2C, SCI, SPI
Length
5 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Width
5 mm
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
1
17.4.3
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
17.4.3.1
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.2
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.3
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.4
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
Freescale Semiconductor
Reset
BDFR is writable only through serial background mode debug commands, not from user programs.
BDFR
Field
W
0
R
DBG Registers and Control Bits
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
0
0
7
Debug Comparator A High Register (DBGCAH)
Debug Comparator A Low Register (DBGCAL)
Debug Comparator B High Register (DBGCBH)
Debug Comparator B Low Register (DBGCBL)
Figure 17-6. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
0
0
6
Table 17-3. SBDFR Register Field Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
0
0
5
0
0
4
Description
0
0
3
2
0
0
0
0
1
Development Support
BDFR
0
0
0
1
259

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