MC9S08QG84CFFER Freescale Semiconductor, MC9S08QG84CFFER Datasheet - Page 49

IC MCU 8BIT 8K FLASH 16-QFN

MC9S08QG84CFFER

Manufacturer Part Number
MC9S08QG84CFFER
Description
IC MCU 8BIT 8K FLASH 16-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08QG84CFFER

Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Data Ram Size
512 B
On-chip Adc
Yes
Number Of Programmable I/os
12
Number Of Timers
1
Mounting Style
SMD/SMT
Height
1 mm
Interface Type
I2C, SCI, SPI
Length
5 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Width
5 mm
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
4.5.1
Features of the FLASH memory include:
4.5.2
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f
200 kHz (see
once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/f
program and erase pulses. An integer number of these timing pulses are used by the command processor
to complete a program or erase command.
Table 4-5
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Freescale Semiconductor
FLASH size
— MC9S08QG8: 8,192 bytes (16 pages of 512 bytes each)
— MC9S08QG4: 4,096 bytes (8 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
Program and Erase Times
FCLK
Features
Section 4.7.1, “FLASH Clock Divider Register
Byte program
Byte program (burst)
Page erase
Mass erase
If the COP is enabled during an erase function, make sure the COP is
serviced during the erase command execution.
1
). The time for one cycle of FCLK is t
Excluding start/end overhead
Parameter
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Table 4-5. Program and Erase Times
Cycles of FCLK
NOTE
20,000
4000
9
4
FCLK
FCLK
) is used by the command processor to time
= 1/f
(FCDIV)”). This register can be written only
FCLK
FCLK
Chapter 4 Memory Map and Register Definition
Time if FCLK = 200 kHz
= 5 μs. Program and erase times
. The times are shown as a number
FCLK
100 ms
20 μs
20 ms
45 μs
) between 150 kHz and
1
47

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