MC908QY4ACDTER Freescale Semiconductor, MC908QY4ACDTER Datasheet - Page 133
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MC908QY4ACDTER
Manufacturer Part Number
MC908QY4ACDTER
Description
MCU 8BIT 4K FLASH W/ADC 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QT1ACDWE.pdf
(200 pages)
Specifications of MC908QY4ACDTER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 133 of 200
- Download datasheet (2Mb)
TOIE — TIM Overflow Interrupt Enable Bit
TSTOP — TIM Stop Bit
TRST — TIM Reset Bit
Freescale Semiconductor
If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a
1 to TOF has no effect.
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set.
This read/write bit stops the counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the counter until software clears the TSTOP bit.
Setting this write-only bit resets the counter and the TIM prescaler. Setting TRST has no effect on any
other timer registers. Counting resumes from $0000. TRST is cleared automatically after the counter
is reset and always reads as 0.
These read/write bits select one of the seven prescaler outputs as the input to the counter as
Table 14-1
1 = Counter has reached modulo value
0 = Counter has not reached modulo value
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
1 = Counter stopped
0 = Counter active
1 = Prescaler and counter cleared
0 = No effect
shows.
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode. Also, when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until the
TSTOP bit is cleared.
Setting the TSTOP and TRST bits simultaneously stops the counter at a
value of $0000.PS[2:0] — Prescaler Select Bits
PS2
0
0
0
0
1
1
1
1
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
PS1
0
0
1
1
0
0
1
1
Table 14-1. Prescaler Selection
PS0
0
1
0
1
0
1
0
1
NOTE
NOTE
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
TIM Clock Source
TCLK (if available)
Registers
133
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