MC9S08SH16CTGR Freescale Semiconductor, MC9S08SH16CTGR Datasheet - Page 306

• Manufacturer Part Number: MC9S08SH16CTGR
• Description: MCU 8BIT 16K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH16CTGR

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Package: 16TSSOP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 13
• Interface Type: SCI/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A Electrical Characteristics
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
306
1
2
3
4
5
Num
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t
frequency changes to the untrimmed DCO frequency (f
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
1
2
3
4
5
6
7
C
D
D
D
D
D
D
C
Control Timing
Bus frequency (t
Internal low power oscillator period
External reset pulse width
Reset low drive
IRQ pulse width
Pin interrupt pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Asynchronous path
Synchronous path
Asynchronous path
Synchronous path
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
Slew rate control disabled (PTxSE = 0)
RESET PIN
3
cyc
= 1/f
4
4
2
2
Rating
Bus
DD
2
MC9S08SH32 Series Data Sheet, Rev. 2
)
and 80% V
Table A-13. Control Timing
Figure A-10. Reset Timing
PRELIMINARY
DD
DD
reset
levels. Temperature range –40°C to 125°C.
5
= 5.0V, 25°C unless otherwise stated.
5
= (f
dco_ut
t
extrst
)/4) because TRIM is reset to 0x80 and FTRIM is reset
t
t
t
t
Symbol
ILIH,
ILIH,
Rise
Rise
t
t
t
rstdrv
f
extrst
LPO
Bus
, t
, t
t
t
IHIL
IHIL
Fall
Fall
1.5 x t
1.5 x t
66 x t
Min
800
100
100
100
dc
—
—
—
—
cyc
cyc
cyc
cyc
. After POR reset, the bus clock
Typ
40
75
11
35
—
—
—
Freescale Semiconductor
1
1500
Max
20
—
—
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns