S9S08SG16E1CTL Freescale Semiconductor, S9S08SG16E1CTL Datasheet - Page 29

• Manufacturer Part Number: S9S08SG16E1CTL
• Description: MCU 16K FLASH 28-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG16E1CTL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET
pin is driven low for about 66 bus cycles. The reset circuitry decodes the cause of reset and records it by
setting a corresponding bit in the system reset status register (SRS).
2.2.4
During a power-on-reset (POR) or background debug force reset (see
Debug Force Reset Register
select pin. Immediately after any reset, the pin functions as the background pin and can be used for
background debug communication. The BKGD/MS pin contains an internal pullup device.
If nothing is connected to this pin, the MCU enters normal operating mode at the rising edge of the internal
reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard background
debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug
force reset, which will force the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5
The MC9S08SG32 Series of MCUs support up to 22 general-purpose I/O pins which are shared with
on-chip peripheral functions (timers, serial I/O, ADC, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose
inputs with internal pull-up devices disabled.
Freescale Semiconductor
Background / Mode Select (BKGD/MS)
General-Purpose I/O and Peripheral Ports
•
•
•
This pin does not contain a clamp diode to V
above V
The voltage measured on the internally pulled up RESET pin will not be
pulled to V
V
pullup should be used.
In EMC-sensitive applications, an external RC filter is recommended on
the RESET. See
DD
. If the RESET pin is required to drive to a V
DD
(SBDFR),” for more information), the BKGD/MS pin functions as a mode
.
DD
. The internal gates connected to this pin are pulled to
Figure 2-4
MC9S08SG32 Data Sheet, Rev. 8
for an example.
NOTE
DD
and should not be driven
DD
Section 5.7.2, “System Background
level, an external
Chapter 2 Pins and Connections
29