S9S08SG16E1CTLR Freescale Semiconductor, S9S08SG16E1CTLR Datasheet - Page 84
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S9S08SG16E1CTLR
Manufacturer Part Number
S9S08SG16E1CTLR
Description
IC MCU 8BIT 16KB FLASH 28TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG16E1CTG.pdf
(330 pages)
Specifications of S9S08SG16E1CTLR
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSSOP
Processor Series
S08SG
Core
HCS08
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
S9S08SG16E1CTLRTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6 Parallel Input/Output Control
6.6.1.3
6.6.1.4
84
PTAPE[7:5,
PTASE[7:5,
Reserved
Reserved
Reset:
Reset:
7:5,3:0
7:5,3:0
Field
Field
3:0]
3:0]
5:4
5:4
W
W
R
R
PTAPE7
PTASE7
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Port A Pull Enable Register (PTAPE)
0
Port A Slew Rate Enable Register (PTASE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured to detect
rising edges.
PTAPE6
PTASE6
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
0
0
6
6
Table 6-4. PTAPE Register Field Descriptions
Table 6-5. PTASE Register Field Descriptions
R
R
0
0
5
5
MC9S08SG32 Data Sheet, Rev. 8
NOTE
R
R
0
0
4
4
Description
Description
PTAPE3
PTASE3
3
0
3
0
PTAPE2
PTASE2
0
0
2
2
PTAPE1
PTASE1
Freescale Semiconductor
0
0
1
1
PTAPE0
PTASE0
0
0
0
0
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