S9S08SG16E1MTJ Freescale Semiconductor, S9S08SG16E1MTJ Datasheet
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MC9S08SG32 MC9S08SG16 Data Sheet Now Includes High-Temperature (up to 150 °C) Devices! HCS08 Microcontrollers MC9S08SG32 Rev. 8 5/2010 freescale.com ...
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MC9S08SG32 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • 36-MHz HCS08 CPU for temperatures greater ° than 125 C • HC08 instruction set with added BGND instruction • Support for up to ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2010. All rights reserved. MC9S08SG32 Data Sheet Covers MC9S08SG32 MC9S08SG16 MC9S08SG32 Rev. 8 5/2010 ...
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... AEC Grade 0 from 1.21V to 1.22 V. Removed AEC Grade 0 (red diamond) from 7 10/2009 the Table A-9 ICS Frequency Specifications, Row 9 Total deviation of trimmed DCO output frequency over voltage and temperature so that it is not listed for AEC Grade 0. 6 Description of Changes MC9S08SG32 Data Sheet, Rev PTxSE slew j Freescale Semiconductor ...
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... Revision Revision Number Date 8 5/2010 © Freescale Semiconductor, Inc., 2007-2010. All rights reserved. This product incorporates SuperFlash Freescale Semiconductor Description of Changes • In the A.9 ICS Characteristic table, changed row 9 parameter classification from indicate that these parameters are guaranteed during production testing on each individual device. ...
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... MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Serial Communications Interface (S08SCIV4)..................... 205 Chapter 15 Serial Peripheral Interface (S08SPIV3) ................................ 225 Chapter 16 Timer Pulse-Width Modulator (S08TPMV3) ......................... 241 Chapter 17 Development Support ........................................................... 269 Appendix A Electrical Characteristics...................................................... 291 Appendix B Ordering Information and Mechanical Drawings................ 325 Freescale Semiconductor Contents Title MC9S08SG32 Data Sheet, Rev. 8 Page 9 ...
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... Reset and Interrupt Vector Assignments ......................................................................................... 40 4.3 Register Addresses and Bit Assignments........................................................................................ 41 4.4 RAM................................................................................................................................................ 48 4.5 FLASH ............................................................................................................................................ 48 4.5.1 Features ............................................................................................................................. 49 4.5.2 Program and Erase Times ................................................................................................. 49 4.5.3 Program and Erase Command Execution ......................................................................... 50 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation Chapter 4 Memory MC9S08SG32 Data Sheet, Rev ...
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... System Power Management Status and Control 2 Register (SPMSC2) ........................... 74 6.1 Port Data and Data Direction .......................................................................................................... 77 6.2 Pull-up, Slew Rate, and Drive Strength........................................................................................... 78 6.3 Ganged Output ................................................................................................................................ 79 6.4 Pin Interrupts ................................................................................................................................... 80 6.4.1 Edge-Only Sensitivity ....................................................................................................... 80 12 Title Chapter 5 Chapter 6 Parallel Input/Output Control MC9S08SG32 Data Sheet, Rev. 8 Page Freescale Semiconductor ...
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... HCS08 Instruction Set Summary .................................................................................................. 104 Analog Comparator 5-V (S08ACMPV3) 8.1 Introduction ................................................................................................................................... 115 8.1.1 ACMP Configuration Information .................................................................................. 115 8.1.2 ACMP/TPM Configuration Information......................................................................... 115 8.2 Features ......................................................................................................................................... 117 8.3 Modes of Operation....................................................................................................................... 117 8.4 Block Diagram .............................................................................................................................. 117 Freescale Semiconductor Title Chapter 7 Chapter 8 MC9S08SG32 Data Sheet, Rev. 8 Page 13 ...
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... Automatic Compare Function......................................................................................... 142 9.4.6 MCU Wait Mode Operation............................................................................................ 143 9.4.7 MCU Stop3 Mode Operation.......................................................................................... 143 9.4.8 MCU Stop2 Mode Operation.......................................................................................... 144 9.5 Initialization Information .............................................................................................................. 144 14 Title Chapter 9 ) .................................................................................................... 129 DDA ) ................................................................................................... 129 SSA ) ................................................................................... 129 REFH )..................................................................................... 129 REFL MC9S08SG32 Data Sheet, Rev. 8 Page Freescale Semiconductor ...
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... Internal Clock Source (S08ICSV2) 11.1 Introduction ................................................................................................................................... 171 11.1.1 Module Configuration..................................................................................................... 171 11.1.2 Features ........................................................................................................................... 173 11.1.3 Block Diagram ................................................................................................................ 173 11.1.4 Modes of Operation ........................................................................................................ 174 11.2 External Signal Description .......................................................................................................... 175 11.3 Register Definition ........................................................................................................................ 175 Freescale Semiconductor Title Chapter 10 Chapter 11 MC9S08SG32 Data Sheet, Rev. 8 Page 15 ...
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... RTC Status and Control Register (RTCSC).................................................................... 199 13.3.2 RTC Counter Register (RTCCNT).................................................................................. 200 13.3.3 RTC Modulo Register (RTCMOD) ................................................................................ 200 13.4 Functional Description .................................................................................................................. 200 13.4.1 RTC Operation Example................................................................................................. 201 16 Title Chapter 12 Modulo Timer (S08MTIMV1) Chapter 13 MC9S08SG32 Data Sheet, Rev. 8 Page Freescale Semiconductor ...
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... SPI Control Register 1 (SPIC1) ...................................................................................... 231 15.4.2 SPI Control Register 2 (SPIC2) ...................................................................................... 232 15.4.3 SPI Baud Rate Register (SPIBR).................................................................................... 233 15.4.4 SPI Status Register (SPIS) .............................................................................................. 234 15.4.5 SPI Data Register (SPID)................................................................................................ 235 Freescale Semiconductor Title Chapter 14 Chapter 15 MC9S08SG32 Data Sheet, Rev. 8 Page ...
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... Forcing Active Background ............................................................................................ 269 17.1.2 Features ........................................................................................................................... 270 17.2 Background Debug Controller (BDC) .......................................................................................... 270 17.2.1 BKGD Pin Description ................................................................................................... 271 17.2.2 Communication Details .................................................................................................. 272 17.2.3 BDC Commands ............................................................................................................. 276 17.2.4 BDC Hardware Breakpoint............................................................................................. 278 18 Title Chapter 16 Chapter 17 Development Support MC9S08SG32 Data Sheet, Rev. 8 Page Freescale Semiconductor ...
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... A.14 EMC Performance..........................................................................................................................324 A.14.1 Radiated Emissions..........................................................................................................324 Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................325 B.1.1 Device Numbering Scheme .............................................................................................326 B.2 Package Information and Mechanical Drawings ...........................................................................326 Freescale Semiconductor Title Appendix A Electrical Characteristics Appendix B MC9S08SG32 Data Sheet, Rev. 8 Page ...
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... Section Number 20 Title MC9S08SG32 Data Sheet, Rev. 8 Page Freescale Semiconductor ...
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... Table 1-1. MC9S08SG32 Series Features by MCU and Package Feature FLASH size (bytes) RAM size (bytes) Pin quantity ACMP ADC channels DBG ICS IIC MTIM Pin Interrupts Pin I/O RTC SCI SPI TPM1 channels TPM2 channels XOSC Freescale Semiconductor t MC9S08SG32 MC9S08SG16 32768 16384 1024 yes yes yes yes ...
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... SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD Δ PTB5/TPM1CH1/SS Δ TCLK PTB4/TPM2CH1/MISO Δ TPM1CH0 PTB3/PIB3/MOSI/ADP7 Δ TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 Δ PTC3/ADP11 Δ :Q!A "D Δ PTC1/TPM1CH1/ADP9 Δ PTC0/TPM1CH0/ADP8 Freescale Semiconductor ...
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... Central Processor Unit Inter-Integrated Circuit Internal Clock Source Low Power Oscillator Modulo Timer On-Chip In-Circuit Emulator Real-Time Counter Serial Peripheral Interface Serial Communications Interface Timer Pulse Width Modulator Freescale Semiconductor Table 1-2. Module Versions Module (ACMP) (ADC10) (CPU) (IIC) (ICS) (XOSC) (MTIM) ...
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... MC9S08SG32 Data Sheet, Rev. 8 MTIM SCI SPI IIC FLASH ADC ADC has min and max FLASH has frequency frequency requirements for program requirements.See the and erase operation. See ADC chapter and the electricals appendix electricals appendix for for details. details. Freescale Semiconductor ...
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... PTC4/ADP12 BKGD/MS VDDA/VREFH VSSA/VREFL PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/ADP11 PTC2/ADP10 RESET BKGD/MS V PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/ADP11 PTC2/ADP10 1. 20-Pin TSSOP package not available for the high-temperature rated devices. Freescale Semiconductor 28 1 PTC6/ADP14 2 27 PTC7/ADP15 26 RESET 3 PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP PTA1/PIA1/TPM2CH0/ADP1/ACMP– 24 VDD 5 PTA2/PIA2/SDA/ACMPO/ADP2 23 6 PTA3/PIA3/SCL/ADP3 ...
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... Chapter 2 Pins and Connections BKGD/MS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO 26 PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ RESET 1 16 PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA2/PIA2/SDA/ACMPO/ADP2 PTA3/PIA3/SCL/ADP3 PTB0/PIB0/RxD/ADP4 6 11 PTB1/PIB1/TxD/ADP5 7 10 PTB2/PIB2/SPSCK/ADP6 8 9 PTB3/PIB3/MOSI/ADP7 Figure 2-3. 16-Pin TSSOP MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... MCU. This voltage source supplies power to all DD SS I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Freescale Semiconductor MC9S08SG32 BKGD/MS PORT A ...
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... REFH REFL shares the V pin and these pins are available only SSA REFL Chapter 11, “Internal Clock Source (when used) and R S MC9S08SG32 Data Sheet, Rev. 8 shares the V DDA REFH pin. SS should be low-inductance F Freescale Semiconductor ...
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... Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pull-up devices disabled. Freescale Semiconductor NOTE DD . The internal gates connected to this pin are pulled to Figure 2-4 for an example ...
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... PIB3 MOSI PTB2 PIB2 SPSCK MC9S08SG32 Data Sheet, Rev. 8 Highest Alt 3 Alt 4 Alt 5 ADP13 ADP12 RESET BKGD DDA REFH V V SSA REFL PTC0 5 PTC0 5 PTC0 ADP11 5 PTC0 ADP10 4 5 PTC0 ADP9 4 5 PTC0 ADP8 5 PTC0 ADP7 5 PTC0 ADP6 Freescale Semiconductor Section 2 ...
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... PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out. 6 TPM2CHx pins can be repositioned using T2CHxPS bits in SOPT2, default reset locations are PTA1, PTB4 ACMP and ADC are both enabled, both will have access to the pin. Freescale Semiconductor Priority Lowest Port Pin Alt 1 ...
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... Chapter 2 Pins and Connections 32 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... When encountering a BDC breakpoint • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 (SBDFR)”) 33 ...
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... MCU is operated in run mode for the first time. When the MC9S08SG32 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...
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... STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Freescale Semiconductor Table 3-1. Stop Mode Selection PPDC x Stop modes disabled ...
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... Refer to Mode,” and Section 3.6.1, “Stop3 36 Mode,” for specific information on system behavior in stop modes. MC9S08SG32 Data Sheet, Rev. 8 Table 3-1. Most is below the LVD DD Section 3.6.2, “Stop2 Freescale Semiconductor ...
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... Voltage regulator will BDM is enabled or if LVD is enabled when entering stop3. 7 ERCLKEN and EREFSTEN set in ICSC2, else in standby. For high frequency range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3. Freescale Semiconductor Table 3-2. Stop Mode Behavior Mode Stop2 Off ...
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... Chapter 3 Modes of Operation 38 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... DIRECT PAGE REGISTERS 0x007F 0x0080 0x047F 0x0480 0x17FF 0x1800 HIGH PAGE REGISTERS 0x185F 0x1860 0x7FFF 0x8000 0xFFFF Figure 4-1. MC9S08SG32/MC9S08SG16 Memory Map Freescale Semiconductor 0x0000 0x007F 0x0080 RAM 1024 BYTES 0x047F 0x0480 UNIMPLEMENTED 4992 BYTES 0x17FF 0x1800 0x185F 0x1860 UNIMPLEMENTED ...
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... Chapter 4 Memory 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08SG32 Series. Address (High/Low) 0xFFC0:0xFFC1 0xFFC2:0xFFC3 ...
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... Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode, which requires 4-4, the whole address in column one is shown in bold. In MC9S08SG32 Data Sheet, Rev ...
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... PS CLKSA PS2 PS1 ELS0B ELS0A ELS1B ELS1A Freescale Semiconductor Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 — 0 — — ACMOD0 — — ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 — — 0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 ...
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... Reserved x005F — 0x0060 TPM2SC TOF 0x0061 TPM2CNTH Bit 15 0x0062 TPM2CNTL Bit 7 0x0063 TPM2MODH Bit 15 0x0064 TPM2MODL Bit 7 0x0065 TPM2C0SC CH0F Freescale Semiconductor — — — — — — RXEDGIE 0 SBR12 SBR6 SBR5 SBR4 SCISWAI RSRC M TCIE RIE ILIE TC ...
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... RTCLKS RTIE RTCCNT RTCMOD — — — — — — MC9S08SG32 Data Sheet, Rev ELS1B ELS1A — — — RTCPS — — — — — — Freescale Semiconductor Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — — ...
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... Reserved 0x183F — 0x1840 PTAPE PTAPE7 0x1841 PTASE PTASE7 0x1842 PTADS PTADS7 0x1843 Reserved — 0x1844 PTASC 0 Freescale Semiconductor 4-3, are accessed much less often than other I/O and control registers PIN COP ILOP COPT STOPE 0 COPW 0 ACIC — — ...
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... PTBIF PTBACK PTBIE PTBMOD PTBPS2 PTBPS1 PTBPS0 PTBES2 PTBES1 PTBES0 — — — PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 PTCDS2 PTCDS1 PTCDS0 GNGPS2 GNGPS1 GNGEN — — — — — — — — — Freescale Semiconductor — — — — — ...
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... FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC) to the unsecured state (1:0). Freescale Semiconductor Table 4-4, are located in the FLASH memory. These registers Table 4-4 ...
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... MC9S08SG32 Series usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ...
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... Parameter Byte program Byte program (burst) Page erase Mass erase 1 Excluding start/end overhead Freescale Semiconductor (FCDIV)”). This register can be written only ) is used by the command processor to time FCLK = 1/f FCLK FCLK FCLK Table 4-5. Program and Erase Times ...
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... The command sequence must be completed by clearing FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. 50 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... The next sequential address selects a byte on the same physical row as the current byte being programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. Freescale Semiconductor Note 1: Required only once after reset. WRITE TO FCDIV (Note 1) ...
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... WRITE COMMAND (0x25) TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles before TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) YES FPVIO OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08SG32 Data Sheet, Rev. 8 checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...
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... This address is formed by concatenating FPS7:FPS1 with logic 1 bits as shown. For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected Freescale Semiconductor NVPROT)”). Figure 4-4 ...
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... FOPT register in high-page register space. A user engages security by programming the NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state 54 1 A12 A11 A10 A9 A8 Figure 4-4. Block Protection Mechanism MC9S08SG32 Data Sheet, Rev Freescale Semiconductor ...
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... Mass erase FLASH if necessary. 3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 4 Memory 55 ...
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... Refer to Table 4-3 and Table 4-4 refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.7.1 FLASH Clock Divider Register (FCDIV) Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time. ...
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... MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the background debug interface. SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. For more detailed information about security, refer to Freescale Semiconductor Table 4-7. FLASH Clock Divider Settings DIV f ...
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... Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. FLASH Protection Register (FPROT) 58 Table 4-9. Security States SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure KEYACC Description Section 4. (1) FPS MC9S08SG32 Data Sheet, Rev “Security.” Freescale Semiconductor (1) FPDIS ...
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... Protection Violation Flag — FPVIOL is set automatically when a command is written that attempts to erase or FPVIOL program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. Freescale Semiconductor Description 5 4 FPVIOL FACCERR ...
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... Execution,” for a detailed discussion of FLASH programming and FCMD Table 4-13. FLASH Commands FCMD Equate File Label 0x05 0x20 0x25 mBurstProg 0x40 mPageErase 0x41 mMassErase MC9S08SG32 Data Sheet, Rev. 8 Errors.” FACCERR is cleared by Table 4-13. Refer to Section mBlank mByteProg Freescale Semiconductor ...
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... Illegal address detect (ILAD) - any address in memory map that is listed as unimplemented will produce an illegal address reset • Background debug forced reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS). Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Table 5-2) 61 ...
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... See t in the appendix LPO LPO MC9S08SG32 Data Sheet, Rev. 8 (SOPT1),” (SOPT2),” for additional COP Overflow Count COP is disabled cycles ( cycles (256 cycles (1.024 cycles 16 2 cycles 18 2 cycles Section A.12.1, “Control Timing,” for the Freescale Semiconductor ...
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... ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not recommended for anyone Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control MC9S08SG32 Data Sheet, Rev. 8 ...
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... ACCUMULATOR * 3 3 INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08SG32 Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control MC9S08SG32 Data Sheet, Rev. 8 ...
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... CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 — — LVWIE Low-voltage warning — — — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect — External pin Illegal opcode — — Illegal address Freescale Semiconductor ...
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... Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation.” Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control in Chapter 4, “ ...
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... ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode COP ILOP ILAD Note Note Note Figure 5-2. System Reset Status (SRS) Table 5-3. SRS Register Field Descriptions Description MC9S08SG32 Data Sheet, Rev LVD Freescale Semiconductor ...
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... Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow BDFR an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Table 5-3. SRS Register Field Descriptions Description ...
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... Stop mode enabled. 2 IIC Pin Select — This bit selects the location of the SDA and SCL pins of the IIC module. IICPS 0 SDA on PTA2, SCL on PTA3. 1 SDA on PTB6, SCL on PTB7 STOPE Description Table MC9S08SG32 Data Sheet, Rev IICPS 0 0 5-1. Freescale Semiconductor ...
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... TPM1CH1 Pin Select— This bit selects the location of the TPM1CH1 pin of the TPM1 module. T1CH1PS 0 TPM1CH1 on PTB5. 1 TPM1CH1 on PTC1. 0 TPM1CH0 Pin Select— This bit selects the location of the TPM1CH0 pin of the TPM1 module. T1CH0PS 0 TPM1CH0 on PTA0. 1 TPM1CH0 on PTC0. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ACIC T2CH1PS 0 0 Table 5-6 ...
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... MC9S08SG32 is hard coded to the value 0x01A. See also ID bits ID11 — — Table 5-7. SDIDH Register Field Descriptions Description 5 4 ID5 ID4 0 1 Table 5-8. SDIDL Register Field Descriptions Description MC9S08SG32 Data Sheet, Rev ID10 ID9 Table 5- ID3 ID2 ID1 Table 5-7. Freescale Semiconductor 0 ID8 0 0 ID0 0 ...
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... LVD logic enabled. 0 Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC and ACMP modules. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control LVWIE ...
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... PPDACK 0 Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected. PPDC 0 Stop3 mode enabled. 1 Stop2, partial power down, mode enabled PPDF 1 LVDV LVWV Description Table 5-11. MC9S08SG32 Data Sheet, Rev PPDC PPDACK Unaffected by reset Freescale Semiconductor ...
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... Table 5-11. LVD and LVW trip point typical values LVDV:LVWV 0:0 0:1 1:0 1:1 1 See Electrical Characteristics appendix for minimum and maximum values. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control LVW Trip Point LVD Trip Point LVW0 V = 2.92 V ...
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... Chapter 5 Resets, Interrupts, and General System Control 76 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. Freescale Semiconductor 2-1. The peripheral modules have priority over the general-purpose I/O NOTE Figure MC9S08SG32 Data Sheet, Rev ...
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... Because of this, the EMC emissions may be affected by enabling pins as high drive. 78 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram MC9S08SG32 Data Sheet, Rev. 8 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
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... Ganged output on PTC3-PTC0 not available on 16-pin packages, however PTC0 control registers are still used to control ganged output. 2 When GNGEN = 1, PTC0 is forced to an output, regardless of the value in PTCDD0 in PTCDD. Freescale Semiconductor NOTE Table 2-1 for information on pin priority. Table 6-1. Ganged Output Pin Enable ...
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... The asserted status of a pin is reflected by its associated I/O general purpose data register CLR PORT INTERRUPT FF PTxMOD Figure 6-2. Pin Interrupt Block Diagram NOTE MC9S08SG32 Data Sheet, Rev. 8 BUSCLK PTxACK RESET PTxIF SYNCHRONIZER STOP BYPASS PTx STOP INTERRUPT REQUEST PTxIE Freescale Semiconductor ...
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... PPDACK bit in the SPMSC2 register. Access to I/O is now permitted again in the user application program. • In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon recovery, normal I/O function is available to the user. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 6 Parallel Input/Output Control 81 ...
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... I/O and their pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 82 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... Input (output driver disabled) and reads return the pin value. 3:0] 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. 5:4 Reserved Bits — These bits are unused on this MCU, writes have no affect and could read 0s. Reserved Freescale Semiconductor PTAD3 ...
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... Output slew rate control enabled for port A bit n. 5:4 Reserved Bits — These bits are unused on this MCU, writes have no affect and could read 0s. Reserved PTAPE3 Description NOTE PTASE3 Description MC9S08SG32 Data Sheet, Rev PTAPE2 PTAPE1 PTAPE0 PTASE2 PTASE1 PTASE0 Freescale Semiconductor ...
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... Port A interrupt request not enabled. 1 Port A interrupt request enabled. 0 Port A Detection Mode — PTAMOD (along with the PTAES bits) controls the detection mode of the port A PTAMOD interrupt pins. 0 Port A pins detect edges only. 1 Port A pins detect both edges and levels. Freescale Semiconductor PTADS3 0 ...
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... A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation PTAPS3 Description PTAES3 Description MC9S08SG32 Data Sheet, Rev PTAPS2 PTAPS1 PTAPS0 PTAES2 PTAES1 PTAES0 Freescale Semiconductor ...
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... Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. Freescale Semiconductor PTBD5 ...
Page 88
... PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit PTBPE5 PTBPE4 PTBPE3 Description NOTE PTBSE5 PTBSE4 PTBSE3 Description MC9S08SG32 Data Sheet, Rev PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 Freescale Semiconductor ...
Page 89
... Port B interrupt request not enabled. 1 Port B interrupt request enabled. 0 Port B Detection Mode — PTBMOD (along with the PTBES bits) controls the detection mode of the port B PTBMOD interrupt pins. 0 Port B pins detect edges only. 1 Port B pins detect both edges and levels. Freescale Semiconductor PTBDS5 PTBDS4 PTBDS3 0 ...
Page 90
... A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation PTBPS3 Description PTBES3 Description MC9S08SG32 Data Sheet, Rev PTBPS2 PTBPS1 PTBPS0 PTBES2 PTBES1 PTBES0 Freescale Semiconductor ...
Page 91
... Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for PTCDD[7:0] PTCD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. Freescale Semiconductor PTCD5 ...
Page 92
... PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit PTCPE5 PTCPE4 PTCPE3 Description PTCSE5 PTCSE4 PTCSE3 Description MC9S08SG32 Data Sheet, Rev PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 Freescale Semiconductor ...
Page 93
... Associated pin is part of the ganged output drive. Requires GNGEN = 1. 0 Ganged Output Drive Enable Bit— This write-once control bit selects whether the ganged output drive feature GNGEN is enabled. 0 Ganged output drive disabled. 1 Ganged output drive enabled. PTC0 forced to output regardless of the value of PTCDD0 in PTCDD. Freescale Semiconductor PTCDS5 PTCDS4 PTCDS3 ...
Page 94
... Chapter 6 Parallel Input/Output Control 94 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 95
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 96
... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 97
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) MC9S08SG32 Data Sheet, Rev. 8 ...
Page 98
... No carry out of bit 7 1 Carry out of bit CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 99
... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) MC9S08SG32 Data Sheet, Rev. 8 ...
Page 100
... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 100 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 101
... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Resets, Interrupts, and System Configuration MC9S08SG32 Data Sheet, Rev ...
Page 102
... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 102 chapter for more details. MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 103
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) MC9S08SG32 Data Sheet, Rev. 8 ...
Page 104
... B4 dd rpp prpp prpp – – ↕ ↕ – rpp 3 F4 rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 77 rfwp 6 ff prfwpp Freescale Semiconductor ...
Page 105
... Branch if Less Than (if N ⊕ (Signed) BLT rel BMC rel Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Object Code REL 24 rr DIR (b0 DIR (b1) 13 ...
Page 106
... Freescale Semiconductor ...
Page 107
... DEC oprx8,SP Divide DIV A ← (H:A)÷(X); H ← Remainder EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP Freescale Semiconductor Object Code IMM A1 DIR B1 EXT C1 IX2 D1 IX1 SP2 ...
Page 108
... rpp prpp prpp – – ↕ ↕ – rpp 3 FE rfp pprpp 4 ff prpp rfwpp ↕ – – ↕ ↕ ↕ rfwpp 4 78 rfwp 6 ff prfwpp rfwpp ↕ – – 0 ↕ ↕ rfwpp 4 74 rfwp 6 ff prfwpp Freescale Semiconductor ...
Page 109
... Rotate Left through Carry ROLA ROLX C ROL oprx8,X b7 ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8 ROR ,X ROR oprx8,SP Freescale Semiconductor Object Code DIR/DIR 4E DIR/IX+ 5E IMM/DIR 6E IX+/DIR 7E INH 42 M ← – (M) = $00 – (M) DIR 30 INH 40 X ← ...
Page 110
... Freescale Semiconductor ...
Page 111
... Test for Negative or Zero TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV3) Object Code IMM A0 ii DIR B0 dd EXT IX2 ...
Page 112
... Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: ↕ Set or cleared – Not affected U Undefined MC9S08SG32 Data Sheet, Rev. 8 Affecton CCR Cyc-by-Cyc Details – – – – – – – – 0 – – – fp... Freescale Semiconductor ...
Page 113
... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...
Page 114
... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...
Page 115
... The ACMP module can be configured to connect the output of the analog comparator to TPM1 input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPM1CH0 pin is not available externally regardless of the configuration of the TPM1 module for channel 0. Freescale Semiconductor Section 5.7.6, “System Power Management Status and Control 1 Section A.6, “DC MC9S08SG32 Data Sheet, Rev. 8 Characteristics” ...
Page 116
... CONVERTER (ADC) MC9S08SG32 Data Sheet, Rev. 8 BKGD/MS RESET PTA7/TPM2CH1 PTA6/TPM2CH0 PTA3/PIA3/SCL/ADP3 PTA2/PIA2/SDA/ACMPO/ADP2 PTA1/PIA1/TPM2CH0/ADP1/ACMP– PTA0/PIA0/TPM1CH0/TCLK/ADP0/ACMP+ PTB7/SCL/EXTAL PTB6/SDA/XTAL Δ PTB5/TPM1CH1/SS Δ PTB4/TPM2CH1/MISO Δ PTB3/PIB3/MOSI/ADP7 Δ PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 PTB0/PIB0/RxD/ADP4 PTC7/ADP15 PTC6/ADP14 PTC5/ADP13 PTC4/ADP12 Δ PTC3/ADP11 Δ PTC2/ADP10 Δ PTC1/TPM1CH1/ADP9 Δ PTC0/TPM1CH0/ADP8 Freescale Semiconductor ...
Page 117
... ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 8.4 Block Diagram The block diagram for the Analog Comparator module is shown Freescale Semiconductor Chapter 8 Analog Comparator 5-V (S08ACMPV3) Figure MC9S08SG32 Data Sheet, Rev. 8 8-2. ...
Page 118
... Chapter 8 Analog Comparator 5-V (S08ACMPV3) Internal Reference ACMP+ ACMP- Figure 8-2. Analog Comparator 5V (ACMP5) Block Diagram 118 Internal Bus ACBGS Status & Control ACME Register + Interrupt Control - Comparator MC9S08SG32 Data Sheet, Rev. 8 ACMP INTERRUPT REQUEST ACIE ACF ACOPE ACMPO Freescale Semiconductor ...
Page 119
... Refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all ACMP registers.This section refers to registers and control bits only by their names. Some MCUs may have more than one ACMP, so register names include placeholder characters to identify which ACMP is being referenced. Freescale Semiconductor Table 8-1. Table 8-1. Signal Properties Function Inverting analog input to the ACMP ...
Page 120
... Analog Comparator Mode — ACMOD selects the type of compare event which sets ACF. ACMOD 00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge 120 ACO ACF ACIE Description MC9S08SG32 Data Sheet, Rev ACOPE ACMOD Freescale Semiconductor ...
Page 121
... The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPO pin using ACOPE. Freescale Semiconductor Chapter 8 Analog Comparator 5-V (S08ACMPV3) MC9S08SG32 Data Sheet, Rev. 8 ...
Page 122
... Chapter 8 Analog Comparator 5-V (S08ACMPV3) 122 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 123
... AD9 PTC1/ADP9 01010 AD10 PTC2/ADP10 01011 AD11 PTC3/ADP11 01100 AD12 PTC4/ADP12 01101 AD13 PTC5/ADP13 01110 AD14 PTC6/ADP14 Freescale Semiconductor NOTE Table 9-1. ADC Channel Assignment Input ADCH PTA0/AD0 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 ...
Page 124
... A.6, “DC Characteristics”. in this chapter correspond to signals V ) after being divided down from the ALTCLK input as ADCK . For value of bandgap voltage, see DD MC9S08SG32 Data Sheet, Rev. 8 Channel Input Module Disabled None (SPMSC1)”. and V , respectively. DDA SSA Section A.6, “DC Freescale Semiconductor ...
Page 125
... Once determined if the temperature is above or below 25°C, the user can recalculate the temperature using the hot or cold slope value obtained during calibration. Freescale Semiconductor , convert the digital value of AD26 into a voltage ÷ ...
Page 126
... MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD Δ PTB5/TPM1CH1/SS Δ TCLK PTB4/TPM2CH1/MISO Δ TPM1CH0 PTB3/PIB3/MOSI/ADP7 Δ TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 Δ PTC3/ADP11 Δ PTC2/ADP10 Δ PTC1/TPM1CH1/ADP9 Δ PTC0/TPM1CH0/ADP8 Freescale Semiconductor ...
Page 127
... ADC module 1. Number of analog inputs varies according to the device and may be from external or internal sources. Refer to the introduction section to this chapter for AD0–AD27 channel input assignments. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SG32 Data Sheet, Rev. 8 ...
Page 128
... Table 9-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL Analog power supply V DDA V Analog ground SSA MC9S08SG32 Data Sheet, Rev. 8 Async Clock Gen ADACK Bus Clock ÷2 ALTCLK 1 AIEN Interrupt 2 COCO 3 Freescale Semiconductor ...
Page 129
... Configuration register, ADCCFG • Pin control registers, APCTLx 1. Number of APCTLx registers depends on the number of external analog inputs available on the device. Please refer to the introduction of this module for external analog input assignments. Freescale Semiconductor ) DDA as its power connection. In some packages, V DDA ...
Page 130
... ADCH 00000 00001 00010 00011 130 ADCO Description Table 9-4. Table 9-4. Input Channel Select Input Select AD0 AD1 AD2 AD3 MC9S08SG32 Data Sheet, Rev ADCH ADCH Input Select 10000 AD16 10001 AD17 10010 AD18 10011 AD19 Freescale Semiconductor ...
Page 131
... When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected Freescale Semiconductor Table 9-4. Input Channel Select (continued) Input Select AD4 AD5 ...
Page 132
... In 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion data into the result registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, 132 Description prior to storage in ADCRH:ADCRL registers prior to storage in ADCRH:ADCRL registers. MC9S08SG32 Data Sheet, Rev ADR9 ADR8 Freescale Semiconductor ...
Page 133
... Figure 9-8. Compare Value Low Register (ADCCVL) 9.3.7 Configuration Register (ADCCFG) ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and long sample time. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1 ADR5 ADR4 ADR3 ...
Page 134
... Table 9-7. Clock Divide Select Divide Ratio Table 9-8. Conversion Modes Mode Description 8-bit conversion (N=8) Reserved 10-bit conversion (N=10) Reserved MC9S08SG32 Data Sheet, Rev MODE ADICLK Table 9-8. Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor ...
Page 135
... ADC Pin Control 2 — ADPC2 controls the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Table 9-9. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 ...
Page 136
... AD11 pin I/O control disabled 2 ADC Pin Control 10 — ADPC10 controls the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled 136 Description ADPC13 ADPC12 ADPC11 Description MC9S08SG32 Data Sheet, Rev ADPC10 ADPC9 ADPC8 Freescale Semiconductor ...
Page 137
... AD19 pin I/O control enabled 1 AD19 pin I/O control disabled 2 ADC Pin Control 18 — ADPC18 controls the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Description ADPC21 ...
Page 138
... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC does not perform according to specifications. If the available clocks 138 Description MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 139
... In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SG32 Data Sheet, Rev. 8 139 ...
Page 140
... ADLSMP selects between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successive 140 MC9S08SG32 Data Sheet, Rev After f ADCK Freescale Semiconductor ...
Page 141
... MHz, then the conversion time for a single conversion is: Conversion time = Number of bus cycles = 3.5 μ MHz = 28 cycles The ADCK frequency must be between f maximum to meet ADC specifications. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) frequency, precise sample time for continuous conversions ADCK ADICLK ...
Page 142
... Then the conversion result of 0x080 is added to 2’s complement of 0x200: %000 1000 0000 + %110 0000 0000 --------------- %110 1000 0000 142 NOTE <= 1’s complement of 0x200 compare value <= 2’s complement of 0x200 compare value <= Subtraction result is –0x180 in signed 11-bit data MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 143
... ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) MC9S08SG32 Data Sheet, Rev. 8 143 ...
Page 144
... Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. 144 NOTE Section 9.4.4.2, “Completing NOTE MC9S08SG32 Data Sheet, Rev. 8 Table 9-7, Table 9-8, and Table 9-9 Freescale Semiconductor ...
Page 145
... AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) Configures for low power (lowers maximum clock speed) Sets the ADCK to the input clock ÷ 1 ...
Page 146
... READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE and V DDA SS and V must be connected to the same voltage potential DDA SSA and V ) and must be routed carefully for maximum DD SS MC9S08SG32 Data Sheet, Rev available as separate pins on SSA on some devices. On other devices, Freescale Semiconductor ...
Page 147
... ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. Freescale Semiconductor may be connected to the same potential as V REFH spec and the V ...
Page 148
... REFH REFL DDA SSA at a quiet point in the ground plane the selected input channel MC9S08SG32 Data Sheet, Rev kept high for less than DDA LEAK . or V (this improves REFL SSA Freescale Semiconductor DD ...
Page 149
... Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1 ...
Page 150
... Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. 150 and increases with noise. This error may be reduced by LSB MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 151
... IICPS in SOPT1 selects which general-purpose I/O ports are associated with IIC operation. IICPS in SOPT1 0 (default) 1 Figure 10-1 shows the MC9S08SG32 Series block diagram with the IIC module highlighted. Freescale Semiconductor NOTE . These pins are pseudo Table 10-1. IIC Position Options ...
Page 152
... MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD Δ PTB5/TPM1CH1/SS Δ TCLK PTB4/TPM2CH1/MISO Δ TPM1CH0 PTB3/PIB3/MOSI/ADP7 Δ TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 Δ PTC3/ADP11 Δ PTC2/ADP10 Δ PTC1/TPM1CH1/ADP9 Δ PTC0/TPM1CH0/ADP8 Freescale Semiconductor ...
Page 153
... Wait mode — The module continues to operate while the MCU is in wait mode and can provide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 10 Inter-Integrated Circuit (S08IICV2) 153 ...
Page 154
... This section consists of the IIC register descriptions in address order. 154 FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 10-2. IIC Functional Block Diagram MC9S08SG32 Data Sheet, Rev. 8 Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...
Page 155
... IIC Frequency Divider Register (IICF MULT W Reset 0 0 Figure 10-4. IIC Frequency Divider Register (IICF) Freescale Semiconductor memory chapter of this document for the absolute address AD5 AD4 AD3 Figure 10-3 ...
Page 156
... MC9S08SG32 Data Sheet, Rev. 8 × SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 10-1 Eqn. 10-2 Eqn. 10-3 Eqn. 10-4 ...
Page 157
... SCL SDA Hold (Start) (hex) Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 Freescale Semiconductor Table 10-5. IIC Divider and Hold Values SCL Hold ICR (Stop) (hex) Value 118 121 3F MC9S08SG32 Data Sheet, Rev. 8 ...
Page 158
... Repeat start. Writing this bit generates a repeated start condition provided it is the current master. This RSTA bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. 158 MST TX TXAK Figure 10-5. IIC Control Register (IICC1) Table 10-6. IICC1 Field Descriptions Description MC9S08SG32 Data Sheet, Rev RSTA Freescale Semiconductor ...
Page 159
... Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after RXAK the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received Freescale Semiconductor BUSY 0 ARBL ...
Page 160
... IIC Control Register 2 (IICC2 GCAEN ADEXT W Reset Unimplemented or Reserved 160 DATA Figure 10-7. IIC Data I/O Register (IICD) Table 10-8. IICD Field Descriptions Description NOTE Figure 10-8. IIC Control Register (IICC2) MC9S08SG32 Data Sheet, Rev AD10 AD9 AD8 Freescale Semiconductor ...
Page 161
... Data transfer • Stop signal The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Freescale Semiconductor Table 10-9. IICC2 Field Descriptions Description Figure MC9S08SG32 Data Sheet, Rev. 8 Chapter 10 Inter-Integrated Circuit (S08IICV2) 10-9 ...
Page 162
... Ack Repeated Bit Start Write Signal Figure 10-9. IIC Bus Transmission Signals MC9S08SG32 Data Sheet, Rev. 8 lsb Data Byte No Ack Signal Bit lsb New Calling Address No Read/ Ack Write Bit Figure 10-9, a start signal is Figure 10-9). Freescale Semiconductor Stop Stop Signal ...
Page 163
... The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, Freescale Semiconductor 10-9. There is one clock pulse on SCL for each data bit, the msb being MC9S08SG32 Data Sheet, Rev ...
Page 164
... SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 164 Delay Figure 10-10. IIC Clock Synchronization MC9S08SG32 Data Sheet, Rev. 8 Figure 10-10). When all Start Counting High Period Freescale Semiconductor ...
Page 165
... After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. Freescale Semiconductor Table 10-10). When a 10-bit address follows a start condition, ...
Page 166
... The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. 166 Table 10-12 Table 10-12. Interrupt Summary Status Flag TCF IICIF IAAS IICIF ARBL IICIF MC9S08SG32 Data Sheet, Rev. 8 occur, provided the IICIE bit Local Enable IICIE IICIE IICIE Freescale Semiconductor ...
Page 167
... A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing it. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 10 Inter-Integrated Circuit (S08IICV2) 167 ...
Page 168
... Module Use can handle both master and slave IIC operations. For slave operation, an Register Model AD[7:1] ICR MST TX TXAK RSTA BUSY ARBL 0 SRW DATA 0 0 AD10 0 Figure 10-11. IIC Module Quick Start MC9S08SG32 Data Sheet, Rev IICIF RXAK AD9 AD8 Freescale Semiconductor ...
Page 169
... When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Freescale Semiconductor Clear IICIF ...
Page 170
... Chapter 10 Inter-Integrated Circuit (S08IICV2) 170 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
Page 171
... When the internal reference is enabled in stop mode (IREFSTEN = 1), the voltage regulator must also be enabled in stop mode by setting the LVDE and LVDSE bits in the SPMSC1 register. Figure 11-1 shows the MC9S08SG32 block diagram with the ICS highlighted. Freescale Semiconductor NOTE for a detailed view of the MC9S08SG32 Data Sheet, Rev. 8 ...
Page 172
... MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD Δ PTB5/TPM1CH1/SS Δ TCLK PTB4/TPM2CH1/MISO Δ TPM1CH0 PTB3/PIB3/MOSI/ADP7 Δ TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 Δ PTC3/ADP11 Δ PTC2/ADP10 Δ PTC1/TPM1CH1/ADP9 Δ PTC0/TPM1CH0/ADP8 Freescale Semiconductor ...
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... HGO, RANGE, EREFS, ERCLKEN, EREFSTEN • FLL Engaged Internal mode is automatically selected out of reset 11.1.3 Block Diagram Figure 11-2 is the ICS block diagram. Freescale Semiconductor 40 ° 125 ° C standard-temperature rated devices MC9S08SG32 Data Sheet, Rev. 8 Chapter 11 Internal Clock Source (S08ICSV2) ° ...
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... FLL. 174 Block ERCLKEN EREFS EREFSTEN IRCLKEN IREFSTEN CLKS Internal LP Reference Clock DCOOUT 9 DCO TRIM 9 n RDIV_CLK Filter FLL Internal Clock Source Block l (FEI) (FEE) l (FBI) MC9S08SG32 Data Sheet, Rev. 8 ICSERCLK ICSIRCLK BDIV ICSOUT n=0-3 ICSLCLK / 2 ICSFFCLK Freescale Semiconductor ...
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... ICS registers. Name 7 R ICSC1 CLKS W R ICSC2 BDIV W R ICSTRM ICSSC W Freescale Semiconductor l Low Power (FBILP) l (FBE) l Low Power (FBELP) Table 11-1. ICS Register Summary RDIV RANGE HGO LP TRIM 0 0 IREFST MC9S08SG32 Data Sheet, Rev. 8 Chapter 11 Internal Clock Source (S08ICSV2) ...
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... Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop 176 5 4 RDIV 0 0 Figure 11-3. ICS Control Register 1 (ICSC1) Description MC9S08SG32 Data Sheet, Rev IREFS IRCLKEN IREFSTEN Freescale Semiconductor 0 0 ...
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... External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock EREFSTEN remains enabled when the ICS enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop Freescale Semiconductor 5 4 RANGE HGO 0 0 Figure 11-4 ...
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... CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected. 10 FLL Bypassed, External reference clock is selected. 11 Reserved. 178 TRIM Figure 11-5. ICS Trim Register (ICSTRM) Description IREFST Description MC9S08SG32 Data Sheet, Rev CLKST OSCINIT FTRIM Freescale Semiconductor ...
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... The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the allowed movements between the states. 11.4.1.1 FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following conditions occur: Freescale Semiconductor Description IREFS=1 CLKS=00 FLL Engaged Internal (FEI) ...
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... BDM mode is not active and LP bit is written FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal reference clock is enabled. 180 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... After a change in the IREFS value the FLL will begin locking again after a few full cycles of the resulting divided reference frequency. The completion of the switch is shown by the IREFST bit. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 11 Internal Clock Source (S08ICSV2) ...
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... ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support (see the Overview chapter). 182 chapter). MC9S08SG32 Data Sheet, Rev. 8 Device Freescale Semiconductor ...
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... ICSFFE will get asserted for the following combinations of BDIV and RDIV values: BDIV=00 (divide by 1), RDIV ≥ 010 • BDIV=01 (divide by 2), RDIV ≥ 011 • BDIV=10 (divide by 4), RDIV ≥ 100 • BDIV=11 (divide by 8), RDIV ≥ 101 • Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 11 Internal Clock Source (S08ICSV2) 183 ...
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... Chapter 11 Internal Clock Source (S08ICSV2) 184 MC9S08SG32 Data Sheet, Rev. 8 Freescale Semiconductor ...
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... The external clock for the MTIM module, TCLK, is selected by setting CLKS = 1:1 or 1:0 in MTIMCLK, which selects the TCLK pin input. The TCLK input can be enabled as external clock inputs to both the MTIM and TPM modules simultaneously. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 185 ...
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... MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD Δ PTB5/TPM1CH1/SS Δ TCLK PTB4/TPM2CH1/MISO Δ TPM1CH0 PTB3/PIB3/MOSI/ADP7 Δ TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 Δ PTC3/ADP11 Δ PTC2/ADP10 Δ PTC1/TPM1CH1/ADP9 Δ PTC0/TPM1CH0/ADP8 Freescale Semiconductor ...
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... The MTIM suspends all counting until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written MTIMMOD written). Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 12 Modulo Timer (S08MTIMV1) 187 ...
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... DIVIDE BY SELECT PS CLKS TOF REG Table 12-1. Signal Properties Function External clock source input into MTIM MC9S08SG32 Data Sheet, Rev. 8 12-2. 8-BIT COUNTER (MTIMCNT) 8-BIT COMPARATOR 8-BIT MODULO (MTIMMOD) Table 12-1. I/O I Pins and Connections chapter for Freescale Semiconductor TRST TSTP ...
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... Refer to the direct-page register summary in the assignments for all MTIM registers.This section refers to registers and control bits only by their names and relative address offsets. Some MCUs may have more than one MTIM, so register names include placeholder characters to identify which MTIM is being referenced. Freescale Semiconductor TOF ...
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... MTIM Counter Stop — When set, this read/write bit stops the MTIM counter at its current value. Counting resumes TSTP from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. 3:0 Unused register bits, always read 0. 190 TSTP TRST Description MC9S08SG32 Data Sheet, Rev Freescale Semiconductor ...
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... Encoding 4. MTIM clock source ÷ 16 0101 Encoding 5. MTIM clock source ÷ 32 0110 Encoding 6. MTIM clock source ÷ 64 0111 Encoding 7. MTIM clock source ÷ 128 1000 Encoding 8. MTIM clock source ÷ 256 All other encodings default to MTIM clock source ÷ 256. Freescale Semiconductor CLKS 0 ...
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... MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to $00 and clears TOF. Reset sets the modulo to $00. 192 COUNT Figure 12-6. MTIM Counter Register Description MOD Figure 12-7. MTIM Modulo Register Description MC9S08SG32 Data Sheet, Rev Freescale Semiconductor ...
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... The MTIM allows for an optional interrupt to be generated whenever TOF is set. To enable the MTIM overflow interrupt, set the MTIM overflow interrupt enable bit (TOIE) in MTIMSC. TOIE should never be written while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 12 Modulo Timer (S08MTIMV1) ...
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... When the counter, MTIMCNT, reaches the modulo value of $AA, the counter overflows to $00 and continues counting. The timer overflow flag, TOF, sets when the counter value changes from $AA to $00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. 194 $A8 $A9 $AA $AA MC9S08SG32 Data Sheet, Rev. 8 $00 $01 Freescale Semiconductor ...
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... This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 195 ...
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... MOSI SPSCK PTB7/SCL/EXTAL RxD PTB6/SDA/XTAL TxD Δ PTB5/TPM1CH1/SS Δ TCLK PTB4/TPM2CH1/MISO Δ TPM1CH0 PTB3/PIB3/MOSI/ADP7 Δ TPM1CH1 PTB2/PIB2/SPSCK/ADP6 PTB1/PIB1/TxD/ADP5 TCLK PTB0/PIB0/RxD/ADP4 TPM2CH0 TPM2CH1 ACMPO ACMP– PTC7/ADP15 ACMP+ PTC6/ADP14 PTC5/ADP13 ADP15-ADP0 PTC4/ADP12 Δ PTC3/ADP11 Δ PTC2/ADP10 Δ PTC1/TPM1CH1/ADP9 Δ PTC0/TPM1CH0/ADP8 Freescale Semiconductor ...
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... The RTC suspends all counting during active background mode until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as the RTCMOD register is not written and the RTCPS and RTCLKS bits are not altered. Freescale Semiconductor MC9S08SG32 Data Sheet, Rev. 8 Chapter 13 Real-Time Counter (S08RTCV1) ...
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... W R RTCMOD W 198 Figure 13-2. 8-Bit Modulo (RTCMOD) 8-Bit Comparator RTC 8-Bit Counter Clock (RTCCNT) Table 13-1. RTC Register Summary RTIF RTCLKS RTIE MC9S08SG32 Data Sheet, Rev RTIF E R RTIE Write 1 to RTIF RTCPS RTCCNT RTCMOD Freescale Semiconductor RTC Interrupt Request 0 ...
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... See counters. Reset clears RTCPS. RTCLKS[ Off Off Freescale Semiconductor 5 4 RTCLKS RTIE 0 0 Table 13-2. RTCSC Field Descriptions Description Table 13-3. Changing the prescaler value clears the prescaler and RTCCNT Table 13-3. RTC Prescaler Divide-by values RTCPS ...
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... The RTC clock select bits (RTCLKS) select the desired clock source different value is written to RTCLKS, the prescaler and RTCCNT counters are reset to 0x00. 200 RTCCNT Table 13-4. RTCCNT Field Descriptions Description RTCMOD Table 13-5. RTCMOD Field Descriptions Description MC9S08SG32 Data Sheet, Rev Freescale Semiconductor ...