S9S08SG16E1MTJ Freescale Semiconductor, S9S08SG16E1MTJ Datasheet - Page 49

• Manufacturer Part Number: S9S08SG16E1MTJ
• Description: MCU 16K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG16E1MTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD. POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.1
Features of the FLASH memory include:
4.5.2
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f
200 kHz (see
once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/f
program and erase pulses. An integer number of these timing pulses are used by the command processor
to complete a program or erase command.
Table 4-5
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Freescale Semiconductor
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FLASH size
— MC9S08SG32: 32,768 bytes (64 pages of 512 bytes each)
— MC9S08SG16: 16,384 bytes (32 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection and vector redirection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
Program and Erase Times
FCLK
Features
Section 4.7.1, “FLASH Clock Divider Register
Byte program
Byte program (burst)
Page erase
Mass erase
1
). The time for one cycle of FCLK is t
Excluding start/end overhead
Parameter
Table 4-5. Program and Erase Times
MC9S08SG32 Data Sheet, Rev. 8
Cycles of FCLK
20,000
4000
9
4
FCLK
FCLK
) is used by the command processor to time
= 1/f
(FCDIV)”). This register can be written only
FCLK
FCLK
Time if FCLK = 200 kHz
= 5 μs. Program and erase times
. The times are shown as a number
FCLK
100 ms
20 μs
20 ms
45 μs
) between 150 kHz and
1
Chapter 4 Memory
49