MC9S08SH8CTJ Freescale Semiconductor, MC9S08SH8CTJ Datasheet - Page 82
![IC MCU 8BIT 8K FLASH 20-TSSOP](/photos/12/34/123427/mc9s08sh8ctj_sml.jpg)
MC9S08SH8CTJ
Manufacturer Part Number
MC9S08SH8CTJ
Description
IC MCU 8BIT 8K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH4CTJ.pdf
(338 pages)
Specifications of MC9S08SH8CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
For Use With
DEMO9S08SH8 - BOARD DEMO FOR MC9S08SH FAM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Chapter 6 Parallel Input/Output Control
6.6.1.4
6.6.1.5
82
PTASE[4:0]
PTADS[4:0]
Reserved
Reserved
Reset:
Reset:
Field
Field
4:0
4:0
5
5
W
W
R
R
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
Port A Slew Rate Enable Register (PTASE)
0
0
Port A Drive Strength Selection Register (PTADS)
0
0
7
7
Figure 6-7. Drive Strength Selection for Port A Register (PTADS)
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
0
0
0
0
6
6
Table 6-5. PTASE Register Field Descriptions
Table 6-6. PTADS Register Field Descriptions
MC9S08SH8 MCU Series Data Sheet, Rev. 3
R
R
0
0
5
5
PTADS4
PTASE4
0
0
4
4
Description
Description
PTADS3
PTASE3
3
0
3
0
PTASE2
PTADS2
0
0
2
2
PTASE1
PTADS1
Freescale Semiconductor
0
0
1
1
PTASE0
PTADS0
0
0
0
0
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