MC908QB4CDWE Freescale Semiconductor, MC908QB4CDWE Datasheet - Page 116
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MC908QB4CDWE
Manufacturer Part Number
MC908QB4CDWE
Description
IC MCU 8BIT 4K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QB8CDWE.pdf
(236 pages)
Specifications of MC908QB4CDWE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Controller Family/series
HC08
No. Of I/o's
14
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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Enhanced Serial Communications Interface (ESCI) Module
13.3.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at these times
(see
To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s.
When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 13-1
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10.
116
•
•
Figure
After every start bit
After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at
RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples
returns a valid 0)
Table 13-2
summarizes the results of the start bit verification samples.
13-6):
RT CLOCK
RT CLOCK
SAMPLES
CLOCK
RESET
STATE
RxD
summarizes the results of the data bit samples.
RT
RT3, RT5, and RT7 Samples
Figure 13-6. Receiver Data Sampling
000
001
010
011
100
101
110
111
QUALIFICATION
Table 13-1. Start Bit Verification
START BIT
MC68HC908QB8 Data Sheet, Rev. 3
VERIFICATION
START BIT
Start Bit Verification
START BIT
Yes
Yes
Yes
Yes
No
No
No
No
SAMPLING
DATA
Noise Flag
0
1
1
0
1
0
0
0
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