C8051F313-GMR Silicon Laboratories Inc, C8051F313-GMR Datasheet - Page 115

• Manufacturer Part Number: C8051F313-GMR
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F313-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
10.4.1. V
10.4.2. PSWE Maintenance
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
2. Make certain that the minimum V
3. Enable the on-chip V
4. As an added precaution, explicitly enable the V
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There
8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
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protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
meet this rise time specification, then add an external V
the device that holds the device in reset until V
drops below 2.7 V.
as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-
based systems, this will involve modifying the startup code added by the 'C' compiler. See your
compiler documentation for more details. Make certain that there are no delays in software
between enabling the V
examples showing this can be found in "AN201: Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
reset source inside the functions that write and erase Flash memory. The V
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one rou-
tine in code that sets PSWE and PSEE both to a '1' to erase Flash pages.
updates and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code
examples showing this can be found in AN201, "Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser-
viced in priority order after the Flash operation has been completed and interrupts have been
re-enabled by software.
Maintenance and the V
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, system clock frequency, or temperature. This accidental execution of Flash modi-
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monitor and enable the V
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monitor and enabling the V
Monitor
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rise time specification of 1 ms is met. If the system cannot
Rev. 1.7
C8051F310/1/2/3/4/5/6/7
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monitor and enable the V
reaches 2.7 V and re-asserts RST if V
monitor as a reset source as early in code
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brownout circuit to the RST pin of
monitor as a reset source. Code
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monitor enable
monitor as a
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