C8051F311-GMR Silicon Laboratories Inc, C8051F311-GMR Datasheet - Page 163

• Manufacturer Part Number: C8051F311-GMR
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F311-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F31x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• For Use With: 336-1446 - ADAPTER PROGRAM TOOLSTICK F311336-1253 - DEV KIT FOR C8051F310/F311
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in
UART0 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Section “15.1. Enhanced Baud Rate Generation” on page
Rate Generator
UART Baud
Write to
SBUF
Figure 15.1. UART0 Block Diagram
Tx Clock
Rx Clock
Stop Bit
Start
Start
SBUF
Read
SCON
D
TB8
SET
CLR
Shift
Input Shift Register
Q
Shift
SFR Bus
(RX Latch)
(9 bits)
Tx Control
Rx Control
SBUF
0x1FF
SFR Bus
Zero Detector
(TX Shift)
SBUF
Rev. 1.7
RB8
Load SBUF
Tx IRQ
Rx IRQ
RI
TI
SBUF
C8051F310/1/2/3/4/5/6/7
Load
Send
Data
Interrupt
Serial
Port
164). Received data buffering allows
TX
RX
Crossbar
Crossbar
Port I/O
163