MCF52110CVM80J Freescale Semiconductor, MCF52110CVM80J Datasheet - Page 20
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MCF52110CVM80J
Manufacturer Part Number
MCF52110CVM80J
Description
IC MCU 128K FLASH 80MHZ 81MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xxr
Datasheet
1.MCF52110CAF80.pdf
(56 pages)
Specifications of MCF52110CVM80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
81-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF52110CVM80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Family Configurations
1.3
Table 4
1.4
Table 5
1.5
Table 6
20
Clock Mode Selection
Reset Configuration
describes signals used to reset the chip or as a reset indication.
describes signals used to support the on-chip clock generation circuitry.
describes signals used in mode selection;
External Clock In
Signal Name
Signal Name
Signal Name
Reset Out
Reset Signals
PLL and Clock Signals
Mode Selection
Clock Out
Reset In
Crystal
Test
CLKMOD[1:0]
00
00
01
10
10
11
Abbreviation
Abbreviation
CLKMOD[1:0] Selects the clock boot mode.
Abbreviation
CLKOUT
RSTO
EXTAL
RSTI
XTAL
RCON
XTAL
TEST
N/A
N/A
0
1
0
1
MCF52110 ColdFire Microcontroller, Rev. 1
Table 6. Mode Selection Signals
Primary reset input to the device. Asserting RSTI for at least 8 CPU
clock cycles immediately resets the CPU and peripherals.
Driven low for 1024 CPU clocks after the reset source has deasserted.
Table 5. PLL and Clock Signals
PLL disabled, clock driven by external oscillator
PLL disabled, clock driven by on-chip oscillator
PLL disabled, clock driven by crystal
PLL in normal mode, clock driven by external oscillator
Reserved
PLL in normal mode, clock driven by crystal
Crystal oscillator or external clock input except when the on-chip
relaxation oscillator is used.
Crystal oscillator output except when CLKMOD0=0, then sampled as
part of the clock mode selection mechanism.
This output signal reflects the internal system clock.
The Serial Flash Programming mode is entered by asserting the
RCON pin (with the TEST pin negated) as the chip comes out of
reset. During this mode, the EzPort has access to the flash memory
which can be programmed from an external device.
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of
test functions.
Table 7. Clocking Modes
Table 7
Table 4. Reset Signals
2
describes the particular clocking modes.
Configure the clock mode.
Function
Function
Function
1
Freescale Semiconductor
I/O
I/O
I/O
O
O
O
I
I
I
I