MC9S08DZ128CLF Freescale Semiconductor, MC9S08DZ128CLF Datasheet - Page 79
MC9S08DZ128CLF
Manufacturer Part Number
MC9S08DZ128CLF
Description
MCU 8BIT 128K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.MC9S08DV96CLF.pdf
(458 pages)
2.MC9S08DV96CLF.pdf
(4 pages)
3.MC9S08DZ128CLF.pdf
(4 pages)
4.MC9S08DZ96MLL.pdf
(4 pages)
Specifications of MC9S08DZ128CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Package
48LQFP
Family Name
HCS08
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
87
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
24-chx12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ128CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC9S08DV96CLF PDF datasheet
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- MC9S08DZ96MLL PDF datasheet #4
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4.6.11.3
Freescale Semiconductor
EPGMOD
EPGSEL
KEYACC
Reset
Field
Field
SEC
1:0
5
6
5
W
R
EEPROM Sector Mode — When this bit is 0, each sector is split into two pages (4-byte mode). When this bit is
1, each sector is in a single page (8-byte mode).
0 Half of each EEPROM sector is in Page 0 and the other half is in Page 1.
1 Each sector is in a single page.
Security State Code — This 2-bit field determines the security state of the MCU as shown in
the MCU is secure, the contents of RAM, EEPROM and FLASH memory cannot be accessed by instructions
from any unsecured source including the background debug interface. SEC changes to 1:0 after successful
backdoor key entry or a successful blank check of FLASH. For more detailed information about security, refer to
Section 4.6.9,
EEPROM Page Select — This bit selects which EEPROM page is accessed in the memory map.
0 Page 0 is in foreground of memory map. Page 1 is in background and can not be accessed.
1 Page 1 is in foreground of memory map. Page 0 is in background and can not be accessed.
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
FLASH and EEPROM Configuration Register (FCNFG)
0
0
7
Figure 4-16. FLASH and EEPROM Configuration Register (FCNFG)
= Unimplemented or Reserved
EPGSEL
“Security.”
0
6
1
Table 4-17. FCNFG Register Field Descriptions
SEC changes to 1:0 after successful backdoor key entry
or a successful blank check of FLASH.
Table 4-15. FOPT Register Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
KEYACC
SEC[1:0]
0
5
0:0
0:1
1:0
1:1
Table 4-16. Security States
1
1
4
Description
Description
Section 4.6.9,
Description
unsecured
secure
secure
secure
3
0
0
1
“Security.”
0
0
2
0
0
1
Table
Chapter 4 Memory
4-16. When
1
1
0
79
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