MC908GR16VFAE Freescale Semiconductor, MC908GR16VFAE Datasheet - Page 130
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MC908GR16VFAE
Manufacturer Part Number
MC908GR16VFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908GR16VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR16VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Input/Output Ports (PORTS)
PTCPUE1 and PTCPUE0 — Port C Input Pullup Enable Bits
12.5 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and three of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
12.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
PTD7–PTD0 — Port D Data Bits
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
SPSCK — SPI Serial Clock
MOSI — Master Out/Slave In
MISO — Master In/Slave Out
130
These writable bits are software programmable to enable pullup devices on an input port bit.
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
The PTD6/T2CH0–PTD7/T2CH1 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD6/T2CH0–PTD7/T2CH1 pins are timer
channel I/O pins or general-purpose I/O pin. See
The PTD4/T1CH0–PTD5/T1CH1 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD4/T1CH0–PTD5/T1CH1 pins are timer
channel I/O pins or general-purpose I/O pins. See
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
Alternative
Function:
Address:
Reset:
Read:
Write:
T2CH1
$0003
PTD7
Bit 7
Figure 12-13. Port D Data Register (PTD)
T2CH0
PTD6
6
MC68HC908GR16 Data Sheet, Rev. 4.0
T1CH1
PTD5
5
T1CH0
Unaffected by reset
PTD4
4
Chapter 18 Timer Interface Module
Chapter 18 Timer Interface Module
SPSCK
PTD3
3
PTD2
MOSI
2
PTD1
MISO
1
Freescale Semiconductor
PTD0
Bit 0
SS
(TIM).
(TIM).
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